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Jay Chang 86bc3a0abf target/riscv: Restrict midelegh access to S-mode harts ... RISC-V AIA Spec states: "For a machine-level environment, extension Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels. For a supervisor-level environment, extension Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Jay Chang <jay.chang@sifive.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250701030021.99218-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		1 month ago
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insn_trans	riscv: Revert "Generate strided vector loads/stores with tcg nodes."	1 month ago
kvm	target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE	2 months ago
tcg	target: riscv: Add Svrsw60t59b extension support	2 months ago
Kconfig	…
XVentanaCondOps.decode	…
arch_dump.c	…
bitmanip_helper.c	codebase: prepare to remove cpu.h from exec/exec-all.h	5 months ago
common-semi-target.h	…
cpu-param.h	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	5 months ago
cpu-qom.h	target/riscv: Add BOSC's Xiangshan Kunminghu CPU	2 months ago
cpu.c	target: riscv: Add Svrsw60t59b extension support	2 months ago
cpu.h	target/riscv: Make PMP region count configurable	2 months ago
cpu_bits.h	target: riscv: Add Svrsw60t59b extension support	2 months ago
cpu_cfg.h	target/riscv: include default value in cpu_cfg_fields.h.inc	4 months ago
cpu_cfg_fields.h.inc	target: riscv: Add Svrsw60t59b extension support	2 months ago
cpu_helper.c	target: riscv: Add Svrsw60t59b extension support	2 months ago
cpu_user.h	…
cpu_vendorid.h	…
crypto_helper.c	include: Remove 'exec/exec-all.h'	4 months ago
csr.c	target/riscv: Restrict midelegh access to S-mode harts	1 month ago
debug.c	include: Remove 'exec/exec-all.h'	4 months ago
debug.h	…
fpu_helper.c	target/riscv: Fix fcvt.s.bf16 NaN box checking	2 months ago
gdbstub.c	target/riscv: store RISCVCPUDef struct directly in the class	4 months ago
helper.h	target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction	2 months ago
insn16.decode	…
insn32.decode	target/riscv: Fix the rvv reserved encoding of unmasked instructions	4 months ago
instmap.h	…
internals.h	target/riscv: Fix MEPC/SEPC bit masking for IALIGN	2 months ago
m128_helper.c	include: Remove 'exec/exec-all.h'	4 months ago
machine.c	target/riscv: Make PMP region count configurable	2 months ago
meson.build	…
monitor.c	…
op_helper.c	target/riscv: do not call GETPC() in check_ret_from_m_mode()	1 month ago
pmp.c	target/riscv: Fix pmp range wraparound on zero	1 month ago
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	8 months ago
pmu.c	include/exec: Split out icount.h	5 months ago
pmu.h	…
riscv-qmp-cmds.c	target/riscv: add profile->present flag	2 months ago
sbi_ecall_interface.h	…
th_csr.c	target/riscv: generalize custom CSR functionality	4 months ago
time_helper.c	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	2 months ago
time_helper.h	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	2 months ago
trace-events	target/riscv: add trace in riscv_raise_exception()	8 months ago
trace.h	…
translate.c	target/riscv: support atomic instruction fetch (Ziccif)	2 months ago
vcrypto_helper.c	include: Remove 'exec/exec-all.h'	4 months ago
vector_helper.c	qemu: Declare all load/store helper in 'qemu/bswap.h'	2 months ago
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	6 months ago
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	6 months ago
xthead.decode	…
zce_helper.c	include: Remove 'exec/exec-all.h'	4 months ago