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Stefan Hajnoczi 98721058d6 * target/i386/kvm: Intel TDX support ... * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model -----BEGIN PGP SIGNATURE----- iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== =XmkU -----END PGP SIGNATURE----- Merge tag 'for-upstream' of https://gitlab.com/bonzini/qemu into staging * target/i386/kvm: Intel TDX support * target/i386/emulate: more lflags cleanups * meson: remove need for explicit listing of dependencies in hw_common_arch and target_common_arch * rust: small fixes * hpet: Reorganize register decoding to be more similar to Rust code * target/i386: fixes for AMD models * target/i386: new EPYC-Turin CPU model # -----BEGIN PGP SIGNATURE----- # # iQFIBAABCgAyFiEE8TM4V0tmI4mGbHaCv/vSX3jHroMFAmg4BxwUHHBib256aW5p # QHJlZGhhdC5jb20ACgkQv/vSX3jHroP67gf+PEP4EDQP0AJUfxXYVsczGf5snGjz # ro8jYmKG+huBZcrS6uPK5zHYxtOI9bHr4ipTHJyHd61lyzN6Ys9amPbs/CRE2Q4x # Ky4AojPhCuaL2wHcYNcu41L+hweVQ3myj97vP3hWvkatulXYeMqW3/4JZgr4WZ69 # A9LGLtLabobTz5yLc8x6oHLn/BZ2y7gjd2LzTz8bqxx7C/kamjoDrF2ZHbX9DLQW # BKWQ3edSO6rorSNHWGZsy9BE20AEkW2LgJdlV9eXglFEuEs6cdPKwGEZepade4bQ # Rdt2gHTlQdUDTFmAbz8pttPxFGMC9Zpmb3nnicKJpKQAmkT/x4k9ncjyAQ== # =XmkU # -----END PGP SIGNATURE----- # gpg: Signature made Thu 29 May 2025 03:05:00 EDT # gpg: using RSA key F13338574B662389866C7682BFFBD25F78C7AE83 # gpg: issuer "pbonzini@redhat.com" # gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full] # gpg: aka "Paolo Bonzini <pbonzini@redhat.com>" [full] # Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4 E2F7 7E15 100C CD36 69B1 # Subkey fingerprint: F133 3857 4B66 2389 866C 7682 BFFB D25F 78C7 AE83 * tag 'for-upstream' of https://gitlab.com/bonzini/qemu: (77 commits) target/i386/tcg/helper-tcg: fix file references in comments target/i386: Add support for EPYC-Turin model target/i386: Update EPYC-Genoa for Cache property, perfmon-v2, RAS and SVM feature bits target/i386: Add couple of feature bits in CPUID_Fn80000021_EAX target/i386: Update EPYC-Milan CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC-Rome CPU model for Cache property, RAS, SVM feature bits target/i386: Update EPYC CPU model for Cache property, RAS, SVM feature bits rust: make declaration of dependent crates more consistent docs: Add TDX documentation i386/tdx: Validate phys_bits against host value i386/tdx: Make invtsc default on i386/tdx: Don't treat SYSCALL as unavailable i386/tdx: Fetch and validate CPUID of TD guest target/i386: Print CPUID subleaf info for unsupported feature i386: Remove unused parameter "uint32_t bit" in feature_word_description() i386/cgs: Introduce x86_confidential_guest_check_features() i386/tdx: Define supported KVM features for TDX i386/tdx: Add XFD to supported bit of TDX i386/tdx: Add supported CPUID bits relates to XFAM i386/tdx: Add supported CPUID bits related to TD Attributes ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>		4 weeks ago
..
insn_trans	target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions	1 month ago
kvm	kvm: Introduce kvm_arch_pre_create_vcpu()	1 month ago
tcg	target/riscv: Fill in TCGCPUOps.pointer_wrap	1 month ago
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	9 months ago
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	3 years ago
arch_dump.c	include: Rename sysemu/ -> system/	6 months ago
bitmanip_helper.c	codebase: prepare to remove cpu.h from exec/exec-all.h	2 months ago
common-semi-target.h	semihosting: Split out common-semi-target.h	3 years ago
cpu-param.h	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	2 months ago
cpu-qom.h	target/riscv: convert SiFive U models to RISCVCPUDef	1 month ago
cpu.c	target/riscv: remove .instance_post_init	1 month ago
cpu.h	target/riscv: generalize custom CSR functionality	1 month ago
cpu_bits.h	target/riscv: Fix the hpmevent mask	4 months ago
cpu_cfg.h	target/riscv: include default value in cpu_cfg_fields.h.inc	1 month ago
cpu_cfg_fields.h.inc	target/riscv: include default value in cpu_cfg_fields.h.inc	1 month ago
cpu_helper.c	target/riscv: fix endless translation loop on big endian systems	1 month ago
cpu_user.h	target/riscv: zicfilp `lpad` impl and branch tracking	8 months ago
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2 years ago
crypto_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
csr.c	target/riscv: generalize custom CSR functionality	1 month ago
debug.c	include: Remove 'exec/exec-all.h'	2 months ago
debug.h	target/riscv: Add textra matching condition for the triggers	9 months ago
fpu_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
gdbstub.c	target/riscv: store RISCVCPUDef struct directly in the class	1 month ago
helper.h	target/riscv: Add CTR sctrclr instruction.	4 months ago
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	8 months ago
insn32.decode	target/riscv: Fix the rvv reserved encoding of unmasked instructions	1 month ago
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	3 years ago
internals.h	target/riscv: Move insn_len to internals.h	1 month ago
m128_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
machine.c	target/riscv: store RISCVCPUDef struct directly in the class	1 month ago
meson.build	riscv: thead: Add th.sxstatus CSR emulation	1 year ago
monitor.c	target/riscv: remove break after g_assert_not_reached()	9 months ago
op_helper.c	target/riscv: Pass ra to riscv_csrrw_i128	1 month ago
pmp.c	target/riscv: pmp: remove redundant check in pmp_is_locked	1 month ago
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	5 months ago
pmu.c	include/exec: Split out icount.h	2 months ago
pmu.h	target/riscv: More accurately model priv mode filtering.	12 months ago
riscv-qmp-cmds.c	qapi: make most CPU commands unconditionally available	1 month ago
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	1 year ago
th_csr.c	target/riscv: generalize custom CSR functionality	1 month ago
time_helper.c	target/riscv: Stop timer with infinite timecmp	9 months ago
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2 years ago
trace-events	target/riscv: add trace in riscv_raise_exception()	5 months ago
trace.h	trace: switch position of headers to what Meson requires	5 years ago
translate.c	target/riscv: store RISCVCPUDef struct directly in the class	1 month ago
vcrypto_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
vector_helper.c	target/riscv: Fix vslidedown with rvv_ta_all_1s	1 month ago
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	3 months ago
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	3 months ago
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2 years ago
zce_helper.c	include: Remove 'exec/exec-all.h'	2 months ago