You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

Alexandre Ghiti dc8bffc4eb target: riscv: Add Svrsw60t59b extension support ... The Svrsw60t59b extension allows to free the PTE reserved bits 60 and 59 for software to use. Reviewed-by: Deepak Gupta <debug@rivosinc.com> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Nutty Liu<liujingqi@lanxincomputing.com> Message-ID: <20250702-dev-alex-svrsw60b59b_v2-v2-1-504ddf0f8530@rivosinc.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		1 week ago
..
insn_trans	target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction	1 week ago
kvm	target/riscv: use qemu_chr_fe_write_all() in DBCN_CONSOLE_WRITE_BYTE	1 week ago
tcg	target: riscv: Add Svrsw60t59b extension support	1 week ago
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	9 months ago
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	3 years ago
arch_dump.c	include: Rename sysemu/ -> system/	7 months ago
bitmanip_helper.c	codebase: prepare to remove cpu.h from exec/exec-all.h	3 months ago
common-semi-target.h	semihosting: Split out common-semi-target.h	3 years ago
cpu-param.h	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	3 months ago
cpu-qom.h	target/riscv: Add BOSC's Xiangshan Kunminghu CPU	1 week ago
cpu.c	target: riscv: Add Svrsw60t59b extension support	1 week ago
cpu.h	target/riscv: Make PMP region count configurable	1 week ago
cpu_bits.h	target: riscv: Add Svrsw60t59b extension support	1 week ago
cpu_cfg.h	target/riscv: include default value in cpu_cfg_fields.h.inc	2 months ago
cpu_cfg_fields.h.inc	target: riscv: Add Svrsw60t59b extension support	1 week ago
cpu_helper.c	target: riscv: Add Svrsw60t59b extension support	1 week ago
cpu_user.h	target/riscv: zicfilp `lpad` impl and branch tracking	9 months ago
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2 years ago
crypto_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
csr.c	target/riscv: Fix MEPC/SEPC bit masking for IALIGN	1 week ago
debug.c	include: Remove 'exec/exec-all.h'	2 months ago
debug.h	target/riscv: Add textra matching condition for the triggers	9 months ago
fpu_helper.c	target/riscv: Fix fcvt.s.bf16 NaN box checking	1 week ago
gdbstub.c	target/riscv: store RISCVCPUDef struct directly in the class	2 months ago
helper.h	target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction	1 week ago
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	9 months ago
insn32.decode	target/riscv: Fix the rvv reserved encoding of unmasked instructions	2 months ago
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	3 years ago
internals.h	target/riscv: Fix MEPC/SEPC bit masking for IALIGN	1 week ago
m128_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
machine.c	target/riscv: Make PMP region count configurable	1 week ago
meson.build	riscv: thead: Add th.sxstatus CSR emulation	1 year ago
monitor.c	target/riscv: remove break after g_assert_not_reached()	10 months ago
op_helper.c	target/riscv: Fix MEPC/SEPC bit masking for IALIGN	1 week ago
pmp.c	target/riscv: Make PMP region count configurable	1 week ago
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	6 months ago
pmu.c	include/exec: Split out icount.h	3 months ago
pmu.h	target/riscv: More accurately model priv mode filtering.	12 months ago
riscv-qmp-cmds.c	target/riscv: add profile->present flag	1 week ago
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	1 year ago
th_csr.c	target/riscv: generalize custom CSR functionality	2 months ago
time_helper.c	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	1 week ago
time_helper.h	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	1 week ago
trace-events	target/riscv: add trace in riscv_raise_exception()	6 months ago
trace.h	trace: switch position of headers to what Meson requires	5 years ago
translate.c	target/riscv: support atomic instruction fetch (Ziccif)	1 week ago
vcrypto_helper.c	include: Remove 'exec/exec-all.h'	2 months ago
vector_helper.c	target/riscv: Add a property to set vill bit on reserved usage of vsetvli instruction	1 week ago
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	4 months ago
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	4 months ago
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	2 years ago
zce_helper.c	include: Remove 'exec/exec-all.h'	2 months ago