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Peter Maydell 5311599cdc target/riscv: Avoid bad shift in riscv_cpu_do_interrupt() ... In riscv_cpu_do_interrupt() we use the 'cause' value we got out of cs->exception as a shift value. However this value can be larger than 31, which means that "1 << cause" is undefined behaviour, because we do the shift on an 'int' type. This causes the undefined behaviour sanitizer to complain on one of the check-tcg tests: $ UBSAN_OPTIONS=print_stacktrace=1:abort_on_error=1:halt_on_error=1 ./build/clang/qemu-system-riscv64 -M virt -semihosting -display none -device loader,file=build/clang/tests/tcg/riscv64-softmmu/issue1060 ../../target/riscv/cpu_helper.c:1805:38: runtime error: shift exponent 63 is too large for 32-bit type 'int' #0 0x55f2dc026703 in riscv_cpu_do_interrupt /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../target/riscv/cpu_helper.c:1805:38 #1 0x55f2dc3d170e in cpu_handle_exception /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../accel/tcg/cpu-exec.c:752:9 In this case cause is RISCV_EXCP_SEMIHOST, which is 0x3f. Use 1ULL instead to ensure that the shift is in range. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241128103831.3452572-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		1 day ago
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insn_trans	target/riscv: Set vdata.vm field for vector load/store whole register instructions	4 weeks ago
kvm	target/riscv/kvm: Update kvm exts to Linux v6.11	4 weeks ago
tcg	target/riscv: AMO operations always raise store/AMO fault	1 month ago
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	2 months ago
XVentanaCondOps.decode	…
arch_dump.c	target/riscv: Fix format for comments	2 years ago
bitmanip_helper.c	…
common-semi-target.h	…
cpu-param.h	license: Update deprecated SPDX tag GPL-2.0+ to GPL-2.0-or-later	3 months ago
cpu-qom.h	target/riscv: Add max32 CPU for RV64 QEMU	1 month ago
cpu.c	target/riscv: Expose zicfiss extension as a cpu property	1 month ago
cpu.h	target/riscv: AMO operations always raise store/AMO fault	1 month ago
cpu_bits.h	target/riscv: implement zicfiss instructions	1 month ago
cpu_cfg.h	target/riscv: Add zicfiss extension	1 month ago
cpu_helper.c	target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()	1 day ago
cpu_user.h	target/riscv: zicfilp `lpad` impl and branch tracking	1 month ago
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2 years ago
crypto_helper.c	target/riscv: Use accelerated helper for AES64KS1I	1 year ago
csr.c	target/riscv: introduce ssp and enabling controls for zicfiss	1 month ago
debug.c	target/riscv: Add textra matching condition for the triggers	2 months ago
debug.h	target/riscv: Add textra matching condition for the triggers	2 months ago
fpu_helper.c	target/riscv: Fix froundnx.h nanbox check	5 months ago
gdbstub.c	riscv, gdbstub.c: fix reg_width in ricsv_gen_dynamic_vector_feature()	6 months ago
helper.h	target/riscv: Raise exceptions on wrs.nto	6 months ago
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	1 month ago
insn32.decode	target/riscv: implement zicfiss instructions	1 month ago
instmap.h	…
internals.h	target/riscv: mmu changes for zicfiss shadow stack protection	1 month ago
m128_helper.c	target/helpers: Remove unnecessary 'qemu/main-loop.h' header	1 year ago
machine.c	target/riscv: introduce ssp and enabling controls for zicfiss	1 month ago
meson.build	riscv: thead: Add th.sxstatus CSR emulation	6 months ago
monitor.c	target/riscv: remove break after g_assert_not_reached()	2 months ago
op_helper.c	target/riscv: save and restore elp state on priv transitions	1 month ago
pmp.c	target/riscv: Introduce elp state and enabling controls for zicfilp	1 month ago
pmp.h	target/riscv: Introduce elp state and enabling controls for zicfilp	1 month ago
pmu.c	target/riscv: Add asserts for out-of-bound access	4 months ago
pmu.h	target/riscv: More accurately model priv mode filtering.	5 months ago
riscv-qmp-cmds.c	target: Improve error reporting for CpuModelInfo member @props	9 months ago
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	6 months ago
th_csr.c	riscv: thead: Add th.sxstatus CSR emulation	6 months ago
time_helper.c	target/riscv: Stop timer with infinite timecmp	2 months ago
time_helper.h	target/riscv: Simplify type conversion for CPURISCVState	2 years ago
trace-events	…
trace.h	…
translate.c	target/riscv: implement zicfiss instructions	1 month ago
vcrypto_helper.c	target/riscv/vector_helpers: do early exit when vstart >= vl	9 months ago
vector_helper.c	target/riscv: Inline unit-stride ld/st and corresponding functions for performance	4 weeks ago
vector_internals.c	target/riscv: Fix the element agnostic function problem	6 months ago
vector_internals.h	target/riscv/vector_helpers: do early exit when vstart >= vl	9 months ago
xthead.decode	…
zce_helper.c	target/riscv: add support for Zcmt extension	2 years ago