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vhaudiquet b25133d38f target/riscv: Fix endianness swap on compressed instructions ... Three instructions were not using the endianness swap flag, which resulted in a bug on big-endian architectures. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131 Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828 Fixes: e0a3054f18 ("target/riscv: add support for Zcb extension") Signed-off-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Cc: qemu-stable@nongnu.org Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929115543.1648157-1-valentin.haudiquet@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
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insn_trans	target/riscv: Fix endianness swap on compressed instructions	2 weeks ago
kvm	target/riscv/kvm: Use riscv_cpu_is_32bit() when handling SBI_DBCN reg	2 weeks ago
tcg	target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions	2 weeks ago
Kconfig	target/riscv/cpu_helper: Fix linking problem with semihosting disabled	1 year ago
XVentanaCondOps.decode	target/riscv: Add XVentanaCondOps custom extension	4 years ago
arch_dump.c	include: Rename sysemu/ -> system/	10 months ago
bitmanip_helper.c	codebase: prepare to remove cpu.h from exec/exec-all.h	6 months ago
common-semi-target.c	include/semihosting/common-semi: extract common_semi API	2 weeks ago
cpu-param.h	tcg: Remove the TCG_GUEST_DEFAULT_MO definition globally	6 months ago
cpu-qom.h	target/riscv: Add BOSC's Xiangshan Kunminghu CPU	3 months ago
cpu.c	target/riscv: rvv: Replace checking V by checking Zve32x	2 weeks ago
cpu.h	target/riscv: use riscv_csrr in riscv_csr_read	2 weeks ago
cpu_bits.h	target: riscv: Add Svrsw60t59b extension support	3 months ago
cpu_cfg.h	target/riscv: include default value in cpu_cfg_fields.h.inc	5 months ago
cpu_cfg_fields.h.inc	target: riscv: Add Svrsw60t59b extension support	3 months ago
cpu_helper.c	target: riscv: Add Svrsw60t59b extension support	3 months ago
cpu_user.h	target/riscv: zicfilp `lpad` impl and branch tracking	12 months ago
cpu_vendorid.h	target/riscv: add Ventana's Veyron V1 CPU	2 years ago
crypto_helper.c	include: Remove 'exec/exec-all.h'	6 months ago
csr.c	target/riscv: rvv: Replace checking V by checking Zve32x	2 weeks ago
debug.c	include: Remove 'exec/exec-all.h'	6 months ago
debug.h	target/riscv: Add textra matching condition for the triggers	1 year ago
fpu_helper.c	target/riscv: Fix fcvt.s.bf16 NaN box checking	3 months ago
gdbstub.c	target/riscv: store RISCVCPUDef struct directly in the class	5 months ago
helper.h	target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64	2 weeks ago
insn16.decode	target/riscv: compressed encodings for sspush and sspopchk	12 months ago
insn32.decode	target/riscv: Fix the rvv reserved encoding of unmasked instructions	5 months ago
instmap.h	target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt()	3 years ago
internals.h	target/riscv: Fix MEPC/SEPC bit masking for IALIGN	3 months ago
m128_helper.c	include: Remove 'exec/exec-all.h'	6 months ago
machine.c	target/riscv: rvv: Replace checking V by checking Zve32x	2 weeks ago
meson.build	include/semihosting/common-semi: extract common_semi API	2 weeks ago
monitor.c	target/riscv: remove break after g_assert_not_reached()	1 year ago
op_helper.c	target/riscv: Fix ssamoswap error handling	2 weeks ago
pmp.c	target/riscv: Fix pmp range wraparound on zero	3 months ago
pmp.h	target/riscv: Add new CSR fields for S{sn, mn, m}pm extensions as part of Zjpm v1.0	9 months ago
pmu.c	include/exec: Split out icount.h	6 months ago
pmu.h	target/riscv: More accurately model priv mode filtering.	1 year ago
riscv-qmp-cmds.c	target/riscv: rvv: Replace checking V by checking Zve32x	2 weeks ago
sbi_ecall_interface.h	target/riscv/kvm: implement SBI debug console (DBCN) calls	1 year ago
th_csr.c	target/riscv: generalize custom CSR functionality	5 months ago
time_helper.c	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	3 months ago
time_helper.h	target/riscv: Enable/Disable S/VS-mode Timer when STCE bit is changed	3 months ago
trace-events	target/riscv: add trace in riscv_raise_exception()	9 months ago
trace.h	trace: switch position of headers to what Meson requires	5 years ago
translate.c	target/riscv: do not use translator_ldl in opcode_at	2 weeks ago
vcrypto_helper.c	include: Remove 'exec/exec-all.h'	6 months ago
vector_helper.c	target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64	2 weeks ago
vector_internals.c	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	7 months ago
vector_internals.h	target/riscv: refactor VSTART_CHECK_EARLY_EXIT() to accept vl as a parameter	7 months ago
xthead.decode	RISC-V: Adding XTheadFmv ISA extension	3 years ago
zce_helper.c	include: Remove 'exec/exec-all.h'	6 months ago