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Max Chou db21c3eb05 target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions ... Handle the overlap of source registers with different EEWs. Co-authored-by: Anton Blanchard <antonb@tenstorrent.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Signed-off-by: Max Chou <max.chou@sifive.com> Message-ID: <20250408103938.3623486-10-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Cc: qemu-stable@nongnu.org		3 weeks ago
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trans_privileged.c.inc	target/riscv: Add CTR sctrclr instruction.	3 months ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvbf16.c.inc	target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions	3 weeks ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvi.c.inc	target/riscv: Add check for 16-bit aligned PC for different priv versions.	3 months ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvv.c.inc	target/riscv: rvv: Apply vext_check_input_eew to vector indexed load/store instructions	3 weeks ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	11 months ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	1 year ago
trans_rvzce.c.inc	target/riscv: Add support to record CTR entries.	3 months ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	11 months ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	1 year ago
trans_rvzicfiss.c.inc	target/riscv: fixes a bug against `ssamoswap` behavior in M-mode	3 months ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	11 months ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	7 months ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	1 year ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago