You cannot select more than 25 topics Topics must start with a letter or number, can include dashes ('-') and can be up to 35 characters long.

vhaudiquet b25133d38f target/riscv: Fix endianness swap on compressed instructions ... Three instructions were not using the endianness swap flag, which resulted in a bug on big-endian architectures. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3131 Buglink: https://bugs.launchpad.net/ubuntu/+source/qemu/+bug/2123828 Fixes: e0a3054f18 ("target/riscv: add support for Zcb extension") Signed-off-by: Valentin Haudiquet <valentin.haudiquet@canonical.com> Cc: qemu-stable@nongnu.org Reviewed-by: Anton Johansson <anjo@rev.ng> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-ID: <20250929115543.1648157-1-valentin.haudiquet@canonical.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
..
trans_privileged.c.inc	target/riscv: Add CTR sctrclr instruction.	7 months ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	3 years ago
trans_rvbf16.c.inc	target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions	5 months ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvi.c.inc	target/riscv: Add check for 16-bit aligned PC for different priv versions.	7 months ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	3 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvv.c.inc	target/riscv: rvv: Fix vslide1[up|down].vx unexpected result when XLEN=32 and SEW=64	2 weeks ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	1 year ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	1 year ago
trans_rvzce.c.inc	target/riscv: Fix endianness swap on compressed instructions	2 weeks ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	1 year ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	1 year ago
trans_rvzicfiss.c.inc	target/riscv: Fix ssamoswap error handling	2 weeks ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	1 year ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	12 months ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	2 years ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago