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Yu-Ming Chang ffe4db11f8 target/riscv: Add check for 16-bit aligned PC for different priv versions. ... For privilege version 1.12 or newer, C always implies Zca. We can only check ext_zca to allow 16-bit aligned PC addresses. For older privilege versions, we only check C. Signed-off-by: Yu-Ming Chang <yumin686@andestech.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <174184718265.10540.10120024221661781046-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		1 month ago
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trans_privileged.c.inc	target/riscv: Add CTR sctrclr instruction.	2 months ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvbf16.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	1 year ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvi.c.inc	target/riscv: Add check for 16-bit aligned PC for different priv versions.	1 month ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvv.c.inc	target/riscv: Set vdata.vm field for vector load/store whole register instructions	6 months ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	9 months ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	11 months ago
trans_rvzce.c.inc	target/riscv: Add support to record CTR entries.	2 months ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	9 months ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	11 months ago
trans_rvzicfiss.c.inc	target/riscv: fixes a bug against `ssamoswap` behavior in M-mode	1 month ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	9 months ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	6 months ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	1 year ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago