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Max Chou b48381b1ee target/riscv: Set vdata.vm field for vector load/store whole register instructions ... The vm field of the vector load/store whole register instruction's encoding is 1. The helper function of the vector load/store whole register instructions may need the vdata.vm field to do some optimizations. Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20240918171412.150107-2-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		4 weeks ago
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trans_privileged.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvbf16.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	9 months ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvi.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	1 year ago
trans_rvv.c.inc	target/riscv: Set vdata.vm field for vector load/store whole register instructions	4 weeks ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	5 months ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	6 months ago
trans_rvzce.c.inc	target/riscv: Update $ra with current $pc in trans_cm_jalt()	9 months ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	5 months ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	1 year ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	6 months ago
trans_rvzicfiss.c.inc	target/riscv: implement zicfiss instructions	1 month ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	5 months ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	1 month ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	10 months ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago