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Tommy Wu 3157a553ec target/riscv: Add Smrnmi mnret instruction ... This patch adds a new instruction 'mnret'. 'mnret' is an M-mode-only instruction that uses the values in `mnepc` and `mnstatus` to return to the program counter, privilege mode, and virtualization mode of the interrupted context. Signed-off-by: Frank Chang <frank.chang@sifive.com> Signed-off-by: Tommy Wu <tommy.wu@sifive.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250106054336.1878291-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		3 days ago
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trans_privileged.c.inc	target/riscv: Add Smrnmi mnret instruction	3 days ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvbf16.c.inc	target/riscv: enable 'vstart_eq_zero' in the end of insns	10 months ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvi.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	1 year ago
trans_rvv.c.inc	target/riscv: Set vdata.vm field for vector load/store whole register instructions	3 months ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	6 months ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	8 months ago
trans_rvzce.c.inc	target/riscv: Update $ra with current $pc in trans_cm_jalt()	11 months ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	6 months ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	1 year ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	8 months ago
trans_rvzicfiss.c.inc	target/riscv: implement zicfiss instructions	3 months ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	6 months ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	3 months ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	12 months ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago