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Daniel Henrique Barboza 09ac27a9b5 riscv: Revert "Generate strided vector loads/stores with tcg nodes." ... This reverts commit 28c12c1f2f. As reported in [1] this commit is breaking Linux vector code, and although a simpler reproducer was provided, the fix itself isn't trivial due to the amount and the nature of the changes. And we really do not want to keep Linux broken while we work on it. The revert will fix Linux and will give us time to do a proper fix. [1] https://mail.gnu.org/archive/html/qemu-devel/2025-07/msg02525.html Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Tested-by: Eric Biggers <ebiggers@kernel.org> Message-ID: <20250710100525.372985-1-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
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trans_privileged.c.inc	target/riscv: Add CTR sctrclr instruction.	5 months ago
trans_rva.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvb.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvbf16.c.inc	target/riscv: rvv: Apply vext_check_input_eew to vector narrow/widen instructions	3 months ago
trans_rvd.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvf.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvi.c.inc	target/riscv: Add check for 16-bit aligned PC for different priv versions.	5 months ago
trans_rvk.c.inc	target/riscv: Drop tcg_temp_free	2 years ago
trans_rvm.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvv.c.inc	riscv: Revert "Generate strided vector loads/stores with tcg nodes."	2 weeks ago
trans_rvvk.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvzabha.c.inc	target/riscv: Add amocas.[b|h] for Zabha	1 year ago
trans_rvzacas.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvzawrs.c.inc	target/riscv: Raise exceptions on wrs.nto	1 year ago
trans_rvzce.c.inc	target/riscv: Add support to record CTR entries.	5 months ago
trans_rvzcmop.c.inc	target/riscv: Add zcmop extension	1 year ago
trans_rvzfa.c.inc	tcg: Rename cpu_env to tcg_env	2 years ago
trans_rvzfh.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_rvzicbo.c.inc	target/riscv: rvzicbo: Fixup CBO extension register calculation	1 year ago
trans_rvzicfiss.c.inc	target/riscv: fixes a bug against `ssamoswap` behavior in M-mode	5 months ago
trans_rvzicond.c.inc	target/riscv: refactor Zicond support	2 years ago
trans_rvzimop.c.inc	target/riscv: Add zimop extension	1 year ago
trans_svinval.c.inc	target/riscv: update `decode_save_opc` to store extra word2	10 months ago
trans_xthead.c.inc	target/riscv: Enable xtheadsync under user mode	2 years ago
trans_xventanacondops.c.inc	target/riscv: redirect XVentanaCondOps to use the Zicond functions	2 years ago