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Peter Maydell 5311599cdc target/riscv: Avoid bad shift in riscv_cpu_do_interrupt() ... In riscv_cpu_do_interrupt() we use the 'cause' value we got out of cs->exception as a shift value. However this value can be larger than 31, which means that "1 << cause" is undefined behaviour, because we do the shift on an 'int' type. This causes the undefined behaviour sanitizer to complain on one of the check-tcg tests: $ UBSAN_OPTIONS=print_stacktrace=1:abort_on_error=1:halt_on_error=1 ./build/clang/qemu-system-riscv64 -M virt -semihosting -display none -device loader,file=build/clang/tests/tcg/riscv64-softmmu/issue1060 ../../target/riscv/cpu_helper.c:1805:38: runtime error: shift exponent 63 is too large for 32-bit type 'int' #0 0x55f2dc026703 in riscv_cpu_do_interrupt /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../target/riscv/cpu_helper.c:1805:38 #1 0x55f2dc3d170e in cpu_handle_exception /mnt/nvmedisk/linaro/qemu-from-laptop/qemu/build/clang/../../accel/tcg/cpu-exec.c:752:9 In this case cause is RISCV_EXCP_SEMIHOST, which is 0x3f. Use 1ULL instead to ensure that the shift is in range. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Fixes: 1697837ed9 ("target/riscv: Add M-mode virtual interrupt and IRQ filtering support.") Fixes: 40336d5b1d ("target/riscv: Add HS-mode virtual interrupt and IRQ filtering support.") Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20241128103831.3452572-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		21 hours ago
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alpha	target/alpha: Explicitly set 2-NaN propagation rule	4 weeks ago
arm	target/arm/tcg/: fix typo in FEAT name	1 week ago
avr	target/avr: Use explicit little-endian LD/ST API	2 months ago
hexagon	target/hexagon: Use explicit little-endian LD/ST API	2 months ago
hppa	target/hppa: Explicitly set 2-NaN propagation rule	4 weeks ago
i386	hvf: complete 1G page support	6 days ago
loongarch	target/loongarch: Explicitly set 2-NaN propagation rule	4 weeks ago
m68k	target/m68k: Initialize float_status fields in gdb set/get functions	4 weeks ago
microblaze	Misc HW patch queue	4 weeks ago
mips	target-arm queue:	4 weeks ago
openrisc	target/openrisc: Explicitly set 2-NaN propagation rule	4 weeks ago
ppc	target/ppc: Fix THREAD_SIBLING_FOREACH for multi-socket	1 week ago
riscv	target/riscv: Avoid bad shift in riscv_cpu_do_interrupt()	21 hours ago
rx	target/rx: Explicitly set 2-NaN propagation rule	4 weeks ago
s390x	target/s390x: Fix the floating-point multiply-and-add NaN rules	2 weeks ago
sh4	license: Update deprecated SPDX tag LGPL-2.0+ to LGPL-2.0-or-later	3 months ago
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Kconfig	target/cris: Remove the deprecated CRIS target	3 months ago
meson.build	target/cris: Remove the deprecated CRIS target	3 months ago