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qemu/target
Richard Henderson f3f2ad1193 target-arm queue:
* Implement FEAT_GCS
  * Implement FEAT_MEC
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Merge tag 'pull-target-arm-20251010' of https://gitlab.com/pm215/qemu into staging

target-arm queue:
 * Implement FEAT_GCS
 * Implement FEAT_MEC

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# gpg: Signature made Fri 10 Oct 2025 06:04:32 AM PDT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [unknown]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [unknown]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [unknown]
# gpg:                 aka "Peter Maydell <peter@archaic.org.uk>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* tag 'pull-target-arm-20251010' of https://gitlab.com/pm215/qemu: (76 commits)
  target/arm: Enable FEAT_MEC in -cpu max
  target/arm: Implement FEAT_MEC registers
  target/arm: Add a cpreg flag to indicate no trap in NV
  tests/tcg/aarch64: Add gcsss
  tests/tcg/aarch64: Add gcspushm
  tests/tcg/aarch64: Add gcsstr
  linux-user/aarch64: Enable GCS in HWCAP
  linux-user/aarch64: Generate GCS signal records
  linux-user/aarch64: Inject SIGSEGV for GCS faults
  target/arm: Enable GCSPR_EL0 for read in user-mode
  linux-user/aarch64: Implement map_shadow_stack syscall
  linux-user/aarch64: Release gcs stack on thread exit
  linux-user/aarch64: Allocate new gcs stack on clone
  linux-user/aarch64: Implement prctls for GCS
  target/arm: Enable FEAT_GCS with -cpu max
  target/arm: Implement EXLOCK check during exception return
  target/arm: Copy EXLOCKEn to EXLOCK on exception to the same EL
  target/arm: Load gcs record for RET with PAuth
  target/arm: Load gcs record for RET
  target/arm: Add gcs record for BLR with PAuth
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 days ago
..
alpha target/alpha: Simplify call_pal implementation 3 weeks ago
arm target/arm: Enable FEAT_MEC in -cpu max 3 days ago
avr treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 4 weeks ago
hexagon accel/tcg: Move cpu_get_tb_cpu_state to TCGCPUOps 6 months ago
hppa target/hppa: Adjust mmu indexes to begin with 0 3 weeks ago
i386 * i386: fix migration issues in 10.1 4 days ago
loongarch target/loongarch: Define loongarch_exception_name() as static 4 days ago
m68k add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2 months ago
microblaze add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2 months ago
mips target/mips: fix TLB huge page check to use 64-bit shift 1 month ago
openrisc treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 4 weeks ago
ppc target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask 2 weeks ago
riscv target/riscv: Fix endianness swap on compressed instructions 2 weeks ago
rx treewide: clear bits of cs->interrupt_request with cpu_reset_interrupt() 4 weeks ago
s390x target/s390x: Replace legacy cpu_physical_memory_[un]map() calls (3/3) 3 days ago
sh4 add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide 2 months ago
sparc target/sparc: Relax decode of rs2_or_imm for v7 3 weeks ago
tricore target: Use cpu_pointer_wrap_uint32 for 32-bit targets 5 months ago
xtensa target/xtensa: replace FSF postal address with licenses URL 4 months ago
Kconfig target/cris: Remove the deprecated CRIS target 1 year ago
meson.build target/cris: Remove the deprecated CRIS target 1 year ago