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146 lines
3.8 KiB
C
146 lines
3.8 KiB
C
/*
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* QEMU RISC-V CPU -- internal functions and types
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*
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* Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef RISCV_CPU_INTERNALS_H
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#define RISCV_CPU_INTERNALS_H
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#include "hw/registerfields.h"
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/*
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* The current MMU Modes are:
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* - U 0b000
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* - S 0b001
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* - S+SUM 0b010
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* - M 0b011
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* - U+2STAGE 0b100
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* - S+2STAGE 0b101
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* - S+SUM+2STAGE 0b110
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* - Shadow stack+U 0b1000
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* - Shadow stack+S 0b1001
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*/
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#define MMUIdx_U 0
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#define MMUIdx_S 1
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#define MMUIdx_S_SUM 2
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#define MMUIdx_M 3
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#define MMU_2STAGE_BIT (1 << 2)
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#define MMU_IDX_SS_WRITE (1 << 3)
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static inline int mmuidx_priv(int mmu_idx)
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{
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int ret = mmu_idx & 3;
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if (ret == MMUIdx_S_SUM) {
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ret = PRV_S;
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}
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return ret;
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}
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static inline bool mmuidx_sum(int mmu_idx)
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{
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return (mmu_idx & 3) == MMUIdx_S_SUM;
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}
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static inline bool mmuidx_2stage(int mmu_idx)
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{
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return mmu_idx & MMU_2STAGE_BIT;
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}
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/* share data between vector helpers and decode code */
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FIELD(VDATA, VM, 0, 1)
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FIELD(VDATA, LMUL, 1, 3)
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FIELD(VDATA, VTA, 4, 1)
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FIELD(VDATA, VTA_ALL_1S, 5, 1)
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FIELD(VDATA, VMA, 6, 1)
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FIELD(VDATA, NF, 7, 4)
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FIELD(VDATA, WD, 7, 1)
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/* float point classify helpers */
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target_ulong fclass_h(uint64_t frs1);
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target_ulong fclass_s(uint64_t frs1);
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target_ulong fclass_d(uint64_t frs1);
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#ifndef CONFIG_USER_ONLY
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extern const VMStateDescription vmstate_riscv_cpu;
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#endif
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enum {
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RISCV_FRM_RNE = 0, /* Round to Nearest, ties to Even */
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RISCV_FRM_RTZ = 1, /* Round towards Zero */
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RISCV_FRM_RDN = 2, /* Round Down */
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RISCV_FRM_RUP = 3, /* Round Up */
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RISCV_FRM_RMM = 4, /* Round to Nearest, ties to Max Magnitude */
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RISCV_FRM_DYN = 7, /* Dynamic rounding mode */
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RISCV_FRM_ROD = 8, /* Round to Odd */
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};
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static inline uint64_t nanbox_s(CPURISCVState *env, float32 f)
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{
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/* the value is sign-extended instead of NaN-boxing for zfinx */
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if (env_archcpu(env)->cfg.ext_zfinx) {
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return (int32_t)f;
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} else {
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return f | MAKE_64BIT_MASK(32, 32);
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}
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}
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static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f)
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{
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/* Disable NaN-boxing check when enable zfinx */
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if (env_archcpu(env)->cfg.ext_zfinx) {
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return (uint32_t)f;
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}
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uint64_t mask = MAKE_64BIT_MASK(32, 32);
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if (likely((f & mask) == mask)) {
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return (uint32_t)f;
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} else {
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return 0x7fc00000u; /* default qnan */
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}
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}
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static inline uint64_t nanbox_h(CPURISCVState *env, float16 f)
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{
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/* the value is sign-extended instead of NaN-boxing for zfinx */
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if (env_archcpu(env)->cfg.ext_zfinx) {
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return (int16_t)f;
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} else {
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return f | MAKE_64BIT_MASK(16, 48);
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}
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}
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static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f)
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{
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/* Disable nanbox check when enable zfinx */
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if (env_archcpu(env)->cfg.ext_zfinx) {
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return (uint16_t)f;
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}
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uint64_t mask = MAKE_64BIT_MASK(16, 48);
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if (likely((f & mask) == mask)) {
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return (uint16_t)f;
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} else {
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return 0x7E00u; /* default qnan */
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}
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}
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/* Our implementation of CPUClass::has_work */
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bool riscv_cpu_has_work(CPUState *cs);
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#endif
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