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Max Chou be50ff3a73 target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions ... According to the RISC-V unprivileged specification, the VLEN should be greater or equal to the ELEN. This commit modifies the minimum VLEN based on the vector extensions and introduces a check rule for VLEN and ELEN. Extension Minimum VLEN * V 128 * Zve64[d|f|x] 64 * Zve32[f|x] 32 Signed-off-by: Max Chou <max.chou@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250923090729.1887406-3-max.chou@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
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meson.build	…
tcg-cpu.c	target/riscv: rvv: Modify minimum VLEN according to enabled vector extensions	2 weeks ago
tcg-cpu.h	target/riscv: Remove AccelCPUClass::cpu_class_init need	6 months ago