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cea82f8cdd
For the fmpyadd instruction on the hppa architecture, there is a bit used to specify whether the instruction is operating on a 32 bit or 64 bit floating point register. For most instructions, such a bit is 0 when operating on the smaller register and 1 when operating on the larger register. However, according to page 6-57 of the PA-RISC 1.1 Architecture and Instruction Set Reference Manual, this convention is reversed for the fmpyadd instruction specifically, meaning the bit is 1 for operations on 32 bit registers and 0 for 64 bit registers. See also page 6-18 (fig. 6-8) and 6-19 (table 6-16), where the f field for FMPYADD and FMPYSUB is documented. Previously, QEMU decoded this operation as operating on the other size of register, leading to bugs when translating the fmpyadd instruction. This patch fixes that issue. Reported-by: Andreas Hüttel <andreas.huettel@ur.de> Signed-off-by: Gabriel Brookman <brookmangabriel@gmail.com> Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3096 Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Acked-by: Helge Deller <deller@gmx.de> Message-ID: <20251009-hppa-correct-fmpyadd-size-bit-decoding-v1-1-f63bb6c3290c@gmail.com> [PMD: Add documentation refs mentioned by Andreas K. Huettel] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> |
4 days ago | |
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| .. | ||
| Kconfig | 4 years ago | |
| cpu-param.h | 6 months ago | |
| cpu-qom.h | 2 years ago | |
| cpu.c | 2 months ago | |
| cpu.h | 4 days ago | |
| fpu_helper.c | 5 months ago | |
| gdbstub.c | 1 year ago | |
| helper.c | 4 days ago | |
| helper.h | 9 months ago | |
| insns.decode | 4 days ago | |
| int_helper.c | 5 months ago | |
| machine.c | 6 months ago | |
| mem_helper.c | 4 days ago | |
| meson.build | 2 years ago | |
| op_helper.c | 6 months ago | |
| sys_helper.c | 6 months ago | |
| trace-events | 4 days ago | |
| trace.h | 5 years ago | |
| translate.c | 4 days ago | |