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qemu/tcg
Peter Maydell 8377e3fb85 tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc()
In simd_desc() we create a SIMD descriptor from various pieces
including an arbitrary data value from the caller.  We try to
sanitize these to make sure everything will fit: the 'data' value
needs to fit in the SIMD_DATA_BITS (== 22) sized field.  However we
do that sanitizing with:
   tcg_debug_assert(data == sextract32(data, 0, SIMD_DATA_BITS));

This works for the case where the data is supposed to be considered
as a signed integer (which can then be returned via simd_data()).
However, some callers want to treat the data value as unsigned.

Specifically, for the Arm SVE operations, make_svemte_desc()
assembles a data value as a collection of fields, and it needs to use
all 22 bits.  Currently if MTE is enabled then its MTEDESC SIZEM1
field may have the most significant bit set, and then it will trip
this assertion.

Loosen the assertion so that we only check that the data value will
fit into the field in some way, either as a signed or as an unsigned
value.  This means we will fail to detect some kinds of bug in the
callers, but we won't spuriously assert for intentional use of the
data field as unsigned.

Cc: qemu-stable@nongnu.org
Fixes: db432672dc ("tcg: Add generic vector expanders")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2601
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <20241115172515.1229393-1-peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
3 weeks ago
..
aarch64 tcg/aarch64: Support TCG_TARGET_HAS_tst_vec 7 months ago
arm include/exec/memop: Rename get_alignment_bits 2 months ago
i386 tcg/i386: Implement vector TST{EQ,NE} for avx512 2 months ago
loongarch64 tcg/loongarch64: remove break after g_assert_not_reached() 2 months ago
mips tcg: Add TCGConst argument to tcg_target_const_match 10 months ago
ppc tcg/ppc: Fix tcg_out_rlw_rc 1 month ago
riscv tcg/riscv: Enable native vector support for TCG host 1 month ago
s390x tcg/s390x: fix constraint for 32-bit TSTEQ/TSTNE 2 months ago
sparc64 include/exec/memop: Rename get_alignment_bits 2 months ago
tci tcg/tci: Support TCG_COND_TST{EQ,NE} 10 months ago
debuginfo.c accel/tcg: Move perf and debuginfo support to tcg/ 10 months ago
meson.build meson: Drop the .fa library suffix 5 months ago
optimize.c tcg/optimize: Optimize bitsel_vec 2 months ago
perf.c accel/tcg: Move perf and debuginfo support to tcg/ 10 months ago
region.c tcg: Make the cleanup-on-error path unique 11 months ago
tcg-common.c tcg: Silent -Wmissing-field-initializers warning 2 years ago
tcg-internal.h tcg: Export vec_gen_6 2 months ago
tcg-ldst.c.inc tcg: Move TCGLabelQemuLdst to tcg.c 2 years ago
tcg-op-gvec.c tcg: Allow top bit of SIMD_DATA_BITS to be set in simd_desc() 3 weeks ago
tcg-op-ldst.c include/exec/memop: Rename get_alignment_bits 2 months ago
tcg-op-vec.c tcg: Export vec_gen_6 2 months ago
tcg-op.c tcg: Propagate new TCGOp to add_as_label_use 2 months ago
tcg-pool.c.inc tcg: Introduce tcg_splitwx_to_{rx,rw} 4 years ago
tcg.c tcg: Reset data_gen_ptr correctly 1 month ago
tci.c tcg: Make tcg/helper-info.h self-contained 7 months ago