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qemu/tcg/riscv
History
Richard Henderson 169d253e1f tcg/riscv: Fix typo in tgen_extract 
Fix the direction of the shift, introduced when converting
the codebase to TCGOutOp* and small tgen_* helpers.

Fixes: 5a4d034f3c ("tcg: Convert extract to TCGOutOpExtract")
Reported-by: Andrea Bolognani <abologna@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Andrea Bolognani <abologna@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
 		1 month ago
..
tcg-target-con-set.h tcg/riscv: Drop support for add2/sub2 3 months ago
tcg-target-con-str.h tcg: Convert sub to TCGOutOpSubtract 3 months ago
tcg-target-has.h tcg: Remove INDEX_op_qemu_st8_* 3 months ago
tcg-target-mo.h tcg: Split out tcg-target-mo.h 7 months ago
tcg-target-opc.h.inc tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc 7 months ago
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2 years ago
tcg-target.c.inc tcg/riscv: Fix typo in tgen_extract 1 month ago
tcg-target.h tcg: Introduce the 'z' constraint for a hardware zero register 6 months ago