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qemu/tcg/riscv
History
Richard Henderson e726f65867 tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 
These defines never should have been added as they were
never used.  Only 32-bit hosts may have these opcodes and
they have them unconditionally.

Fixes: 6cb14e4de2 ("tcg/loongarch64: Add the tcg-target.h file")
Fixes: fb1f70f368 ("tcg/riscv: Add the tcg-target.h file")
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
 		4 days ago
..
tcg-target-con-set.h tcg/riscv: Use 'z' constraint 4 days ago
tcg-target-con-str.h tcg/riscv: Use 'z' constraint 4 days ago
tcg-target-has.h tcg: Remove TCG_TARGET_HAS_{br,set}cond2 from riscv and loongarch64 4 days ago
tcg-target-mo.h tcg: Split out tcg-target-mo.h 1 month ago
tcg-target-opc.h.inc tcg: Rename tcg-target.opc.h to tcg-target-opc.h.inc 1 month ago
tcg-target-reg-bits.h tcg: Split out tcg-target-reg-bits.h 2 years ago
tcg-target.c.inc tcg/riscv: Use 'z' constraint 4 days ago
tcg-target.h tcg: Introduce the 'z' constraint for a hardware zero register 4 days ago