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${ noResults }
Dani Szebenyi
9a2a5f1b63
tcg/ppc: Fix tcg_out_rlw_rc
The TCG IR sequence: mov_i32 tmp97,$0xc4240000 dead: 1 pref=0xffffffff mov_i32 tmp98,$0x0 pref=0xffffffff rotr_i32 tmp97,tmp97,tmp98 dead: 1 2 pref=0xffffffff was translated to `slwi r15, r14, 0` instead of `slwi r14, r14, 0` due to SH field overflow. SH field is 5 bits, and tcg_out_rlw is called in some situations with `32-n`, when `n` is 0 it results in an overflow to RA field. This commit prevents overflow of that field and adds debug assertions for the other fields Acked-by: Ilya Leoshkevich <iii@linux.ibm.com> Signed-off-by: Dani Szebenyi <szedani@linux.ibm.com> Message-ID: <20241022133535.69351-2-szedani@linux.ibm.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
1 month ago | |
|---|---|---|
| .. | ||
| tcg-target-con-set.h | tcg/ppc: Optimize cmpsel with constant 0/-1 arguments | 2 months ago |
| tcg-target-con-str.h | tcg/ppc: Add TCG_CT_CONST_CMP | 10 months ago |
| tcg-target-reg-bits.h | tcg: Split out tcg-target-reg-bits.h | 2 years ago |
| tcg-target.c.inc | tcg/ppc: Fix tcg_out_rlw_rc | 1 month ago |
| tcg-target.h | tcg/ppc: Implement cmpsel_vec | 2 months ago |
| tcg-target.opc.h | tcg/ppc: Implement INDEX_op_rot[lr]v_vec | 5 years ago |