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d3b96a5319
'mode' will never be RISCV_IOMMU_CAP_SV32. We are erroring out in the
'switch' right before it if 'mode' isn't 0, 8, 9 or 10.
'mode' should be check with RISCV_IOMMU_DC_FSC_IOSATP_MODE_SV32.
Reported by Coverity via a "DEADCODE" ticket.
Resolves: Coverity CID 1564781
Fixes:
|
4 weeks ago | |
---|---|---|
.. | ||
Kconfig | 1 month ago | |
boot.c | 1 month ago | |
meson.build | 1 month ago | |
microchip_pfsoc.c | 2 months ago | |
numa.c | 10 months ago | |
opentitan.c | 2 months ago | |
riscv-iommu-bits.h | 1 month ago | |
riscv-iommu-pci.c | 1 month ago | |
riscv-iommu.c | 4 weeks ago | |
riscv-iommu.h | 1 month ago | |
riscv_hart.c | 4 years ago | |
shakti_c.c | 2 months ago | |
sifive_e.c | 2 months ago | |
sifive_u.c | 1 month ago | |
spike.c | 2 months ago | |
trace-events | 1 month ago | |
trace.h | 1 month ago | |
virt-acpi-build.c | 4 months ago | |
virt.c | 1 month ago |