qemu/riscv at master - qemu

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Stefan Hajnoczi d6430c17d7 Second RISC-V PR for 10.0 * Reduce the overhead for simple RISC-V vector unit-stride loads and stores * Add V bit to GDB priv reg * Add 'sha' support * Add traces for exceptions in user mode * Update Pointer Masking to Zjpm v1.0 * Add Smrnmi support * Fix timebase-frequency when using KVM acceleration * Add RISC-V Counter delegation ISA extension support * Add support for Smdbltrp and Ssdbltrp extensions * Introduce a translation tag for the IOMMU page table cache * Support Supm and Sspm as part of Zjpm v1.0 * Convert htif debug prints to trace event -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmeMUUwACgkQr3yVEwxT gBNgDQ/+JeqcsbJRX+PZQJEV06tDIJpk+mfaBHUYSGdNkjI9fzowNaxFIEB2vaLt 4+xAGMnJ4vMcjJyBcPOn1FKAlowM7MsUNITOF9Rstnyriqnj2UsUZ9YBtkuG6gWH ZHoYEKu7mAZoZw5RRx4TatHDXw7TYfUsrDPrn+x6yeCZTq9ruRTlHkzp2LC725Vq KTnbWAP7WlqiJaSxB5eIFYT5tYP1Blp0yD358B037C57EU9j5zm2FQdFmVK1+xRF dFg/urBIzfAjjkCS/t9DmH+S6NgMEut6udUhllk/KUJAzWvsggc4wZZlWjFOJFJY fIxx3alhY3pcm1PYjFpf15Poz6Pqva/KGjwgZafirKQtPbRSzfRkUwcHOYRTQT9j abeiB44XPaeIl8Jvw7GLxcWtlJ5NmBrZho+2Z9mIhB/Ix5H3PDgs18Oc/s73P2qQ JFLRb7cpYy1HbRc0ugvwAmOTY1t6HX8HAtT+3rNhiXpXnj4RW2C/WU1cEqrg8QkM cTPiy2zHoBhAWt9aDK1Kvbhb1vur3JaF7rk9jeKlriFr87Ly+yPU+8mnEDw40NMR Tc9nivqmOqqXS5AM9O/W1uzTWzpxIUy7XBy3cuSk0uZCoge4IE2Or7P2Rb2uyaNZ RkAo/PL2N1cMjP7gB3kLRtYY7FA+nal66KhfbHPRHqj+ZwUAxzs= =F3IG -----END PGP SIGNATURE----- Merge tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu into staging Second RISC-V PR for 10.0 * Reduce the overhead for simple RISC-V vector unit-stride loads and stores * Add V bit to GDB priv reg * Add 'sha' support * Add traces for exceptions in user mode * Update Pointer Masking to Zjpm v1.0 * Add Smrnmi support * Fix timebase-frequency when using KVM acceleration * Add RISC-V Counter delegation ISA extension support * Add support for Smdbltrp and Ssdbltrp extensions * Introduce a translation tag for the IOMMU page table cache * Support Supm and Sspm as part of Zjpm v1.0 * Convert htif debug prints to trace event # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCAAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmeMUUwACgkQr3yVEwxT # gBNgDQ/+JeqcsbJRX+PZQJEV06tDIJpk+mfaBHUYSGdNkjI9fzowNaxFIEB2vaLt # 4+xAGMnJ4vMcjJyBcPOn1FKAlowM7MsUNITOF9Rstnyriqnj2UsUZ9YBtkuG6gWH # ZHoYEKu7mAZoZw5RRx4TatHDXw7TYfUsrDPrn+x6yeCZTq9ruRTlHkzp2LC725Vq # KTnbWAP7WlqiJaSxB5eIFYT5tYP1Blp0yD358B037C57EU9j5zm2FQdFmVK1+xRF # dFg/urBIzfAjjkCS/t9DmH+S6NgMEut6udUhllk/KUJAzWvsggc4wZZlWjFOJFJY # fIxx3alhY3pcm1PYjFpf15Poz6Pqva/KGjwgZafirKQtPbRSzfRkUwcHOYRTQT9j # abeiB44XPaeIl8Jvw7GLxcWtlJ5NmBrZho+2Z9mIhB/Ix5H3PDgs18Oc/s73P2qQ # JFLRb7cpYy1HbRc0ugvwAmOTY1t6HX8HAtT+3rNhiXpXnj4RW2C/WU1cEqrg8QkM # cTPiy2zHoBhAWt9aDK1Kvbhb1vur3JaF7rk9jeKlriFr87Ly+yPU+8mnEDw40NMR # Tc9nivqmOqqXS5AM9O/W1uzTWzpxIUy7XBy3cuSk0uZCoge4IE2Or7P2Rb2uyaNZ # RkAo/PL2N1cMjP7gB3kLRtYY7FA+nal66KhfbHPRHqj+ZwUAxzs= # =F3IG # -----END PGP SIGNATURE----- # gpg: Signature made Sat 18 Jan 2025 20:11:40 EST # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20250119-1' of https://github.com/alistair23/qemu: (50 commits) hw/char/riscv_htif: Convert HTIF_DEBUG() to trace events target/riscv: Support Supm and Sspm as part of Zjpm v1.0 hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache target/riscv: Add Smdbltrp ISA extension enable switch target/riscv: Implement Smdbltrp behavior target/riscv: Implement Smdbltrp sret, mret and mnret behavior target/riscv: Add Smdbltrp CSRs handling target/riscv: Add Ssdbltrp ISA extension enable switch target/riscv: Implement Ssdbltrp exception handling target/riscv: Implement Ssdbltrp sret, mret and mnret behavior target/riscv: Add Ssdbltrp CSRs handling target/riscv: Fix henvcfg potentially containing stale bits target/riscv: Add configuration for S[m\|s]csrind, Smcdeleg/Ssccfg target/riscv: Add implied rule for counter delegation extensions target/riscv: Invoke pmu init after feature enable target/riscv: Add counter delegation/configuration support target/riscv: Add select value range check for counter delegation target/riscv: Add counter delegation definitions target/riscv: Add properties for counter delegation ISA extensions target/riscv: Support generic CSR indirect access ... Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>		3 days ago
..
Kconfig	hw/riscv: Add Microblaze V generic board	1 month ago
boot.c	Accel & Exec patch queue	1 month ago
meson.build	hw/riscv: Add Microblaze V generic board	1 month ago
microblaze-v-generic.c	Accel & Exec patch queue	1 month ago
microchip_pfsoc.c	Accel & Exec patch queue	1 month ago
numa.c	include: Rename sysemu/ -> system/	1 month ago
opentitan.c	Accel & Exec patch queue	1 month ago
riscv-iommu-bits.h	hw/riscv/riscv-iommu: parametrize CAP.IGS	1 month ago
riscv-iommu-pci.c	RISC-V PR for 10.0	1 month ago
riscv-iommu-sys.c	hw/riscv/riscv-iommu-sys.c: fix duplicated 'table_size'	4 weeks ago
riscv-iommu.c	hw/riscv/riscv-iommu.c: Introduce a translation tag for the page table cache	3 days ago
riscv-iommu.h	hw/riscv/riscv-iommu: implement reset protocol	1 month ago
riscv_hart.c	Second RISC-V PR for 10.0	3 days ago
shakti_c.c	include: Rename sysemu/ -> system/	1 month ago
sifive_e.c	Accel & Exec patch queue	1 month ago
sifive_u.c	Accel & Exec patch queue	1 month ago
spike.c	Accel & Exec patch queue	1 month ago
trace-events	hw/riscv/riscv-iommu: implement reset protocol	1 month ago
trace.h	hw/riscv: add RISC-V IOMMU base emulation	3 months ago
virt-acpi-build.c	Accel & Exec patch queue	1 month ago
virt.c	hw/riscv/virt: Remove unnecessary use of &first_cpu	3 days ago