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131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/*
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* QEMU emulation of an RISC-V IOMMU
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*
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* Copyright (C) 2022-2023 Rivos Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef HW_RISCV_IOMMU_STATE_H
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#define HW_RISCV_IOMMU_STATE_H
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#include "qom/object.h"
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#include "hw/riscv/iommu.h"
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struct RISCVIOMMUState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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uint32_t version; /* Reported interface version number */
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uint32_t pid_bits; /* process identifier width */
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uint32_t bus; /* PCI bus mapping for non-root endpoints */
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uint64_t cap; /* IOMMU supported capabilities */
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uint64_t fctl; /* IOMMU enabled features */
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uint64_t icvec_avail_vectors; /* Available interrupt vectors in ICVEC */
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bool enable_off; /* Enable out-of-reset OFF mode (DMA disabled) */
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bool enable_msi; /* Enable MSI remapping */
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bool enable_ats; /* Enable ATS support */
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bool enable_s_stage; /* Enable S/VS-Stage translation */
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bool enable_g_stage; /* Enable G-Stage translation */
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/* IOMMU Internal State */
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uint64_t ddtp; /* Validated Device Directory Tree Root Pointer */
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dma_addr_t cq_addr; /* Command queue base physical address */
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dma_addr_t fq_addr; /* Fault/event queue base physical address */
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dma_addr_t pq_addr; /* Page request queue base physical address */
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uint32_t cq_mask; /* Command queue index bit mask */
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uint32_t fq_mask; /* Fault/event queue index bit mask */
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uint32_t pq_mask; /* Page request queue index bit mask */
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/* interrupt notifier */
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void (*notify)(RISCVIOMMUState *iommu, unsigned vector);
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/* IOMMU State Machine */
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QemuThread core_proc; /* Background processing thread */
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QemuCond core_cond; /* Background processing wake up signal */
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unsigned core_exec; /* Processing thread execution actions */
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/* IOMMU target address space */
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AddressSpace *target_as;
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MemoryRegion *target_mr;
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/* MSI / MRIF access trap */
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AddressSpace trap_as;
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MemoryRegion trap_mr;
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GHashTable *ctx_cache; /* Device translation Context Cache */
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GHashTable *iot_cache; /* IO Translated Address Cache */
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unsigned iot_limit; /* IO Translation Cache size limit */
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/* MMIO Hardware Interface */
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MemoryRegion regs_mr;
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uint8_t *regs_rw; /* register state (user write) */
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uint8_t *regs_wc; /* write-1-to-clear mask */
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uint8_t *regs_ro; /* read-only mask */
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QLIST_ENTRY(RISCVIOMMUState) iommus;
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QLIST_HEAD(, RISCVIOMMUSpace) spaces;
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};
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void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus,
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Error **errp);
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/* private helpers */
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/* Register helper functions */
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static inline uint32_t riscv_iommu_reg_mod32(RISCVIOMMUState *s,
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unsigned idx, uint32_t set, uint32_t clr)
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{
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uint32_t val = ldl_le_p(s->regs_rw + idx);
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stl_le_p(s->regs_rw + idx, (val & ~clr) | set);
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return val;
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}
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static inline void riscv_iommu_reg_set32(RISCVIOMMUState *s, unsigned idx,
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uint32_t set)
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{
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stl_le_p(s->regs_rw + idx, set);
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}
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static inline uint32_t riscv_iommu_reg_get32(RISCVIOMMUState *s, unsigned idx)
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{
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return ldl_le_p(s->regs_rw + idx);
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}
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static inline uint64_t riscv_iommu_reg_mod64(RISCVIOMMUState *s, unsigned idx,
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uint64_t set, uint64_t clr)
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{
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uint64_t val = ldq_le_p(s->regs_rw + idx);
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stq_le_p(s->regs_rw + idx, (val & ~clr) | set);
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return val;
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}
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static inline void riscv_iommu_reg_set64(RISCVIOMMUState *s, unsigned idx,
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uint64_t set)
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{
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stq_le_p(s->regs_rw + idx, set);
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}
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static inline uint64_t riscv_iommu_reg_get64(RISCVIOMMUState *s,
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unsigned idx)
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{
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return ldq_le_p(s->regs_rw + idx);
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}
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#endif
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