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185 lines
7.2 KiB
C
185 lines
7.2 KiB
C
/*
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* QEMU model of Microblaze V generic board.
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*
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* based on hw/microblaze/petalogix_ml605_mmu.c
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*
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* Copyright (c) 2011 Michal Simek <monstr@monstr.eu>
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* Copyright (c) 2011 PetaLogix
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* Copyright (c) 2009 Edgar E. Iglesias.
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* Copyright (C) 2024, Advanced Micro Devices, Inc.
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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* Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com
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* and by Michal Simek <michal.simek@amd.com>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "hw/sysbus.h"
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#include "system/system.h"
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#include "net/net.h"
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#include "hw/boards.h"
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#include "hw/char/serial-mm.h"
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#include "exec/address-spaces.h"
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#include "hw/char/xilinx_uartlite.h"
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#include "hw/misc/unimp.h"
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#define LMB_BRAM_SIZE (128 * KiB)
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#define MEMORY_BASEADDR 0x80000000
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#define INTC_BASEADDR 0x41200000
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#define TIMER_BASEADDR 0x41c00000
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#define TIMER_BASEADDR2 0x41c10000
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#define UARTLITE_BASEADDR 0x40600000
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#define ETHLITE_BASEADDR 0x40e00000
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#define UART16550_BASEADDR 0x44a10000
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#define AXIENET_BASEADDR 0x40c00000
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#define AXIDMA_BASEADDR 0x41e00000
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#define GPIO_BASEADDR 0x40000000
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#define GPIO_BASEADDR2 0x40010000
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#define GPIO_BASEADDR3 0x40020000
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#define I2C_BASEADDR 0x40800000
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#define QSPI_BASEADDR 0x44a00000
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#define TIMER_IRQ 0
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#define UARTLITE_IRQ 1
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#define UART16550_IRQ 4
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#define ETHLITE_IRQ 5
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#define TIMER_IRQ2 6
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#define AXIENET_IRQ 7
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#define AXIDMA_IRQ1 8
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#define AXIDMA_IRQ0 9
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static void mb_v_generic_init(MachineState *machine)
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{
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ram_addr_t ram_size = machine->ram_size;
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DeviceState *dev, *dma, *eth0;
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Object *ds, *cs;
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int i;
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RISCVCPU *cpu;
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hwaddr ddr_base = MEMORY_BASEADDR;
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MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
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MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
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qemu_irq irq[32];
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MemoryRegion *sysmem = get_system_memory();
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cpu = RISCV_CPU(object_new(machine->cpu_type));
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object_property_set_bool(OBJECT(cpu), "h", false, NULL);
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object_property_set_bool(OBJECT(cpu), "d", false, NULL);
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qdev_realize(DEVICE(cpu), NULL, &error_abort);
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/* Attach emulated BRAM through the LMB. */
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memory_region_init_ram(phys_lmb_bram, NULL,
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"mb_v.lmb_bram", LMB_BRAM_SIZE,
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&error_fatal);
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memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);
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memory_region_init_ram(phys_ram, NULL, "mb_v.ram",
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ram_size, &error_fatal);
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memory_region_add_subregion(sysmem, ddr_base, phys_ram);
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dev = qdev_new("xlnx.xps-intc");
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qdev_prop_set_uint32(dev, "kind-of-intr",
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1 << UARTLITE_IRQ);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0,
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qdev_get_gpio_in(DEVICE(cpu), 11));
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for (i = 0; i < 32; i++) {
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irq[i] = qdev_get_gpio_in(dev, i);
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}
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/* Uartlite */
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dev = qdev_new(TYPE_XILINX_UARTLITE);
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qdev_prop_set_chr(dev, "chardev", serial_hd(0));
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]);
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/* Full uart */
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serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2,
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irq[UART16550_IRQ], 115200, serial_hd(1),
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DEVICE_LITTLE_ENDIAN);
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/* 2 timers at irq 0 @ 100 Mhz. */
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dev = qdev_new("xlnx.xps-timer");
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qdev_prop_set_uint32(dev, "one-timer-only", 0);
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qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]);
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/* 2 timers at irq 3 @ 100 Mhz. */
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dev = qdev_new("xlnx.xps-timer");
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qdev_prop_set_uint32(dev, "one-timer-only", 0);
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qdev_prop_set_uint32(dev, "clock-frequency", 100000000);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]);
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/* Emaclite */
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dev = qdev_new("xlnx.xps-ethernetlite");
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qemu_configure_nic_device(dev, true, NULL);
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qdev_prop_set_uint32(dev, "tx-ping-pong", 0);
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qdev_prop_set_uint32(dev, "rx-ping-pong", 0);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]);
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/* axi ethernet and dma initialization. */
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eth0 = qdev_new("xlnx.axi-ethernet");
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dma = qdev_new("xlnx.axi-dma");
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/* FIXME: attach to the sysbus instead */
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object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0));
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object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma));
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ds = object_property_get_link(OBJECT(dma),
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"axistream-connected-target", NULL);
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cs = object_property_get_link(OBJECT(dma),
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"axistream-control-connected-target", NULL);
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qemu_configure_nic_device(eth0, true, NULL);
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qdev_prop_set_uint32(eth0, "rxmem", 0x1000);
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qdev_prop_set_uint32(eth0, "txmem", 0x1000);
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object_property_set_link(OBJECT(eth0), "axistream-connected", ds,
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&error_abort);
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object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs,
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]);
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ds = object_property_get_link(OBJECT(eth0),
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"axistream-connected-target", NULL);
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cs = object_property_get_link(OBJECT(eth0),
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"axistream-control-connected-target", NULL);
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qdev_prop_set_uint32(dma, "freqhz", 100000000);
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object_property_set_link(OBJECT(dma), "axistream-connected", ds,
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&error_abort);
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object_property_set_link(OBJECT(dma), "axistream-control-connected", cs,
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&error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal);
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sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR);
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sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]);
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sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]);
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/* unimplemented devices */
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create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000);
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create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000);
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create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000);
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create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000);
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create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000);
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}
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static void mb_v_generic_machine_init(MachineClass *mc)
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{
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mc->desc = "AMD Microblaze-V generic platform";
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mc->init = mb_v_generic_init;
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mc->min_cpus = 1;
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mc->max_cpus = 1;
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mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
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mc->default_cpus = 1;
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}
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DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init)
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