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Yang Liu a3ab69f9f6 target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered ... Starting with RVV1.0, the original vf[w]redsum_vs instruction was renamed to vf[w]redusum_vs. The distinction between ordered and unordered is also more consistent with other instructions, although there is no difference in implementation between the two for QEMU. Signed-off-by: Yang Liu <liuyang22@iscas.ac.cn> Acked-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Message-Id: <20220817074802.20765-2-liuyang22@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 years ago
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trans_privileged.c.inc	target/riscv: Honour -semihosting-config userspace=on and enable=on	2 years ago
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	3 years ago
trans_rvb.c.inc	target/riscv: rvk: add support for zbkx extension	3 years ago
trans_rvd.c.inc	target/riscv: add support for zdinx	3 years ago
trans_rvf.c.inc	target/riscv: add support for zfinx	3 years ago
trans_rvh.c.inc	target/riscv: Minimize the calls to decode_save_opc	2 years ago
trans_rvi.c.inc	target/riscv: Add Zihintpause support	2 years ago
trans_rvk.c.inc	target/riscv: rvk: add support for zksed/zksh extension	3 years ago
trans_rvm.c.inc	target/riscv: add support for zmmul extension v0.1	2 years ago
trans_rvv.c.inc	target/riscv: rvv-1.0: vf[w]redsum distinguish between ordered/unordered	2 years ago
trans_rvzfh.c.inc	target/riscv: add support for zhinx/zhinxmin	3 years ago
trans_svinval.c.inc	target/riscv: add support for svinval extension	3 years ago
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	3 years ago