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889 lines
45 KiB
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889 lines
45 KiB
Plaintext
#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rs3 27:5
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%rs2 20:5
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%rs1 15:5
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%rd 7:5
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%sh5 20:5
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%sh6 20:6
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%sh7 20:7
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%csr 20:12
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%rm 12:3
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%nf 29:3 !function=ex_plus_1
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# immediates:
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%imm_i 20:s12
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%imm_s 25:s7 7:5
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%imm_b 31:s1 7:1 25:6 8:4 !function=ex_shift_1
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%imm_j 31:s1 12:8 20:1 21:10 !function=ex_shift_1
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%imm_u 12:s20 !function=ex_shift_12
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%imm_bs 30:2 !function=ex_shift_3
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%imm_rnum 20:4
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# Argument sets:
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&empty
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&b imm rs2 rs1
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&i imm rs1 rd
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&j imm rd
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&r rd rs1 rs2
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&r2 rd rs1
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&r2_s rs1 rs2
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&s imm rs1 rs2
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&u imm rd
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&shift shamt rs1 rd
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&atomic aq rl rs2 rs1 rd
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&rmrr vm rd rs1 rs2
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&rmr vm rd rs2
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&r2nfvm vm rd rs1 nf
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&rnfvm vm rd rs1 rs2 nf
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&k_aes shamt rs2 rs1 rd
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# Formats 32:
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@r ....... ..... ..... ... ..... ....... &r %rs2 %rs1 %rd
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@i ............ ..... ... ..... ....... &i imm=%imm_i %rs1 %rd
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@b ....... ..... ..... ... ..... ....... &b imm=%imm_b %rs2 %rs1
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@s ....... ..... ..... ... ..... ....... &s imm=%imm_s %rs2 %rs1
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@u .................... ..... ....... &u imm=%imm_u %rd
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@j .................... ..... ....... &j imm=%imm_j %rd
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@sh ...... ...... ..... ... ..... ....... &shift shamt=%sh7 %rs1 %rd
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@csr ............ ..... ... ..... ....... %csr %rs1 %rd
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@atom_ld ..... aq:1 rl:1 ..... ........ ..... ....... &atomic rs2=0 %rs1 %rd
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@atom_st ..... aq:1 rl:1 ..... ........ ..... ....... &atomic %rs2 %rs1 %rd
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@r4_rm ..... .. ..... ..... ... ..... ....... %rs3 %rs2 %rs1 %rm %rd
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@r_rm ....... ..... ..... ... ..... ....... %rs2 %rs1 %rm %rd
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@r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd
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@r2 ....... ..... ..... ... ..... ....... &r2 %rs1 %rd
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@r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd
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@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd
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@r1_vm ...... vm:1 ..... ..... ... ..... ....... %rd
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@r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd
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@r2rd ....... ..... ..... ... ..... ....... %rs2 %rd
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@r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd
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@r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd
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@r_vm_0 ...... . ..... ..... ... ..... ....... &rmrr vm=0 %rs2 %rs1 %rd
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@r2_zimm11 . zimm:11 ..... ... ..... ....... %rs1 %rd
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@r2_zimm10 .. zimm:10 ..... ... ..... ....... %rs1 %rd
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@r2_s ....... ..... ..... ... ..... ....... %rs2 %rs1
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@hfence_gvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@hfence_vvma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vma ....... ..... ..... ... ..... ....... %rs2 %rs1
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@sfence_vm ....... ..... ..... ... ..... ....... %rs1
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@k_aes .. ..... ..... ..... ... ..... ....... &k_aes shamt=%imm_bs %rs2 %rs1 %rd
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@i_aes .. ..... ..... ..... ... ..... ....... &i imm=%imm_rnum %rs1 %rd
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# Formats 64:
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@sh5 ....... ..... ..... ... ..... ....... &shift shamt=%sh5 %rs1 %rd
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# Formats 128:
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@sh6 ...... ...... ..... ... ..... ....... &shift shamt=%sh6 %rs1 %rd
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# *** Privileged Instructions ***
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ecall 000000000000 00000 000 00000 1110011
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ebreak 000000000001 00000 000 00000 1110011
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uret 0000000 00010 00000 000 00000 1110011
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sret 0001000 00010 00000 000 00000 1110011
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mret 0011000 00010 00000 000 00000 1110011
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wfi 0001000 00101 00000 000 00000 1110011
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sfence_vma 0001001 ..... ..... 000 00000 1110011 @sfence_vma
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sfence_vm 0001000 00100 ..... 000 00000 1110011 @sfence_vm
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# *** RV32I Base Instruction Set ***
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lui .................... ..... 0110111 @u
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auipc .................... ..... 0010111 @u
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jal .................... ..... 1101111 @j
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jalr ............ ..... 000 ..... 1100111 @i
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beq ....... ..... ..... 000 ..... 1100011 @b
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bne ....... ..... ..... 001 ..... 1100011 @b
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blt ....... ..... ..... 100 ..... 1100011 @b
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bge ....... ..... ..... 101 ..... 1100011 @b
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bltu ....... ..... ..... 110 ..... 1100011 @b
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bgeu ....... ..... ..... 111 ..... 1100011 @b
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lb ............ ..... 000 ..... 0000011 @i
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lh ............ ..... 001 ..... 0000011 @i
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lw ............ ..... 010 ..... 0000011 @i
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lbu ............ ..... 100 ..... 0000011 @i
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lhu ............ ..... 101 ..... 0000011 @i
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sb ....... ..... ..... 000 ..... 0100011 @s
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sh ....... ..... ..... 001 ..... 0100011 @s
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sw ....... ..... ..... 010 ..... 0100011 @s
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addi ............ ..... 000 ..... 0010011 @i
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slti ............ ..... 010 ..... 0010011 @i
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sltiu ............ ..... 011 ..... 0010011 @i
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xori ............ ..... 100 ..... 0010011 @i
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ori ............ ..... 110 ..... 0010011 @i
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andi ............ ..... 111 ..... 0010011 @i
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slli 00000. ...... ..... 001 ..... 0010011 @sh
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srli 00000. ...... ..... 101 ..... 0010011 @sh
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srai 01000. ...... ..... 101 ..... 0010011 @sh
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add 0000000 ..... ..... 000 ..... 0110011 @r
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sub 0100000 ..... ..... 000 ..... 0110011 @r
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sll 0000000 ..... ..... 001 ..... 0110011 @r
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slt 0000000 ..... ..... 010 ..... 0110011 @r
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sltu 0000000 ..... ..... 011 ..... 0110011 @r
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xor 0000000 ..... ..... 100 ..... 0110011 @r
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srl 0000000 ..... ..... 101 ..... 0110011 @r
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sra 0100000 ..... ..... 101 ..... 0110011 @r
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or 0000000 ..... ..... 110 ..... 0110011 @r
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and 0000000 ..... ..... 111 ..... 0110011 @r
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{
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pause 0000 0001 0000 00000 000 00000 0001111
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fence ---- pred:4 succ:4 ----- 000 ----- 0001111
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}
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fence_i ---- ---- ---- ----- 001 ----- 0001111
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csrrw ............ ..... 001 ..... 1110011 @csr
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csrrs ............ ..... 010 ..... 1110011 @csr
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csrrc ............ ..... 011 ..... 1110011 @csr
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csrrwi ............ ..... 101 ..... 1110011 @csr
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csrrsi ............ ..... 110 ..... 1110011 @csr
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csrrci ............ ..... 111 ..... 1110011 @csr
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# *** RV64I Base Instruction Set (in addition to RV32I) ***
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lwu ............ ..... 110 ..... 0000011 @i
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ld ............ ..... 011 ..... 0000011 @i
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sd ....... ..... ..... 011 ..... 0100011 @s
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addiw ............ ..... 000 ..... 0011011 @i
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slliw 0000000 ..... ..... 001 ..... 0011011 @sh5
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srliw 0000000 ..... ..... 101 ..... 0011011 @sh5
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sraiw 0100000 ..... ..... 101 ..... 0011011 @sh5
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addw 0000000 ..... ..... 000 ..... 0111011 @r
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subw 0100000 ..... ..... 000 ..... 0111011 @r
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sllw 0000000 ..... ..... 001 ..... 0111011 @r
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srlw 0000000 ..... ..... 101 ..... 0111011 @r
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sraw 0100000 ..... ..... 101 ..... 0111011 @r
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# *** RV128I Base Instruction Set (in addition to RV64I) ***
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ldu ............ ..... 111 ..... 0000011 @i
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lq ............ ..... 010 ..... 0001111 @i
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sq ............ ..... 100 ..... 0100011 @s
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addid ............ ..... 000 ..... 1011011 @i
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sllid 000000 ...... ..... 001 ..... 1011011 @sh6
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srlid 000000 ...... ..... 101 ..... 1011011 @sh6
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sraid 010000 ...... ..... 101 ..... 1011011 @sh6
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addd 0000000 ..... ..... 000 ..... 1111011 @r
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subd 0100000 ..... ..... 000 ..... 1111011 @r
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slld 0000000 ..... ..... 001 ..... 1111011 @r
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srld 0000000 ..... ..... 101 ..... 1111011 @r
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srad 0100000 ..... ..... 101 ..... 1111011 @r
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# *** RV32M Standard Extension ***
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mul 0000001 ..... ..... 000 ..... 0110011 @r
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mulh 0000001 ..... ..... 001 ..... 0110011 @r
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mulhsu 0000001 ..... ..... 010 ..... 0110011 @r
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mulhu 0000001 ..... ..... 011 ..... 0110011 @r
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div 0000001 ..... ..... 100 ..... 0110011 @r
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divu 0000001 ..... ..... 101 ..... 0110011 @r
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rem 0000001 ..... ..... 110 ..... 0110011 @r
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remu 0000001 ..... ..... 111 ..... 0110011 @r
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# *** RV64M Standard Extension (in addition to RV32M) ***
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mulw 0000001 ..... ..... 000 ..... 0111011 @r
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divw 0000001 ..... ..... 100 ..... 0111011 @r
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divuw 0000001 ..... ..... 101 ..... 0111011 @r
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remw 0000001 ..... ..... 110 ..... 0111011 @r
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remuw 0000001 ..... ..... 111 ..... 0111011 @r
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# *** RV128M Standard Extension (in addition to RV64M) ***
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muld 0000001 ..... ..... 000 ..... 1111011 @r
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divd 0000001 ..... ..... 100 ..... 1111011 @r
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divud 0000001 ..... ..... 101 ..... 1111011 @r
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remd 0000001 ..... ..... 110 ..... 1111011 @r
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remud 0000001 ..... ..... 111 ..... 1111011 @r
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# *** RV32A Standard Extension ***
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lr_w 00010 . . 00000 ..... 010 ..... 0101111 @atom_ld
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sc_w 00011 . . ..... ..... 010 ..... 0101111 @atom_st
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amoswap_w 00001 . . ..... ..... 010 ..... 0101111 @atom_st
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amoadd_w 00000 . . ..... ..... 010 ..... 0101111 @atom_st
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amoxor_w 00100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoand_w 01100 . . ..... ..... 010 ..... 0101111 @atom_st
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amoor_w 01000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomin_w 10000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomax_w 10100 . . ..... ..... 010 ..... 0101111 @atom_st
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amominu_w 11000 . . ..... ..... 010 ..... 0101111 @atom_st
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amomaxu_w 11100 . . ..... ..... 010 ..... 0101111 @atom_st
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# *** RV64A Standard Extension (in addition to RV32A) ***
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lr_d 00010 . . 00000 ..... 011 ..... 0101111 @atom_ld
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sc_d 00011 . . ..... ..... 011 ..... 0101111 @atom_st
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amoswap_d 00001 . . ..... ..... 011 ..... 0101111 @atom_st
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amoadd_d 00000 . . ..... ..... 011 ..... 0101111 @atom_st
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amoxor_d 00100 . . ..... ..... 011 ..... 0101111 @atom_st
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amoand_d 01100 . . ..... ..... 011 ..... 0101111 @atom_st
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amoor_d 01000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomin_d 10000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomax_d 10100 . . ..... ..... 011 ..... 0101111 @atom_st
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amominu_d 11000 . . ..... ..... 011 ..... 0101111 @atom_st
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amomaxu_d 11100 . . ..... ..... 011 ..... 0101111 @atom_st
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# *** RV32F Standard Extension ***
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flw ............ ..... 010 ..... 0000111 @i
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fsw ....... ..... ..... 010 ..... 0100111 @s
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fmadd_s ..... 00 ..... ..... ... ..... 1000011 @r4_rm
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fmsub_s ..... 00 ..... ..... ... ..... 1000111 @r4_rm
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fnmsub_s ..... 00 ..... ..... ... ..... 1001011 @r4_rm
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fnmadd_s ..... 00 ..... ..... ... ..... 1001111 @r4_rm
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fadd_s 0000000 ..... ..... ... ..... 1010011 @r_rm
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fsub_s 0000100 ..... ..... ... ..... 1010011 @r_rm
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fmul_s 0001000 ..... ..... ... ..... 1010011 @r_rm
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fdiv_s 0001100 ..... ..... ... ..... 1010011 @r_rm
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fsqrt_s 0101100 00000 ..... ... ..... 1010011 @r2_rm
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fsgnj_s 0010000 ..... ..... 000 ..... 1010011 @r
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fsgnjn_s 0010000 ..... ..... 001 ..... 1010011 @r
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fsgnjx_s 0010000 ..... ..... 010 ..... 1010011 @r
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fmin_s 0010100 ..... ..... 000 ..... 1010011 @r
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fmax_s 0010100 ..... ..... 001 ..... 1010011 @r
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fcvt_w_s 1100000 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_wu_s 1100000 00001 ..... ... ..... 1010011 @r2_rm
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fmv_x_w 1110000 00000 ..... 000 ..... 1010011 @r2
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feq_s 1010000 ..... ..... 010 ..... 1010011 @r
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flt_s 1010000 ..... ..... 001 ..... 1010011 @r
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fle_s 1010000 ..... ..... 000 ..... 1010011 @r
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fclass_s 1110000 00000 ..... 001 ..... 1010011 @r2
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fcvt_s_w 1101000 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_s_wu 1101000 00001 ..... ... ..... 1010011 @r2_rm
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fmv_w_x 1111000 00000 ..... 000 ..... 1010011 @r2
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# *** RV64F Standard Extension (in addition to RV32F) ***
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fcvt_l_s 1100000 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_lu_s 1100000 00011 ..... ... ..... 1010011 @r2_rm
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fcvt_s_l 1101000 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_s_lu 1101000 00011 ..... ... ..... 1010011 @r2_rm
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# *** RV32D Standard Extension ***
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fld ............ ..... 011 ..... 0000111 @i
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fsd ....... ..... ..... 011 ..... 0100111 @s
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fmadd_d ..... 01 ..... ..... ... ..... 1000011 @r4_rm
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fmsub_d ..... 01 ..... ..... ... ..... 1000111 @r4_rm
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fnmsub_d ..... 01 ..... ..... ... ..... 1001011 @r4_rm
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fnmadd_d ..... 01 ..... ..... ... ..... 1001111 @r4_rm
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fadd_d 0000001 ..... ..... ... ..... 1010011 @r_rm
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fsub_d 0000101 ..... ..... ... ..... 1010011 @r_rm
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fmul_d 0001001 ..... ..... ... ..... 1010011 @r_rm
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fdiv_d 0001101 ..... ..... ... ..... 1010011 @r_rm
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fsqrt_d 0101101 00000 ..... ... ..... 1010011 @r2_rm
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fsgnj_d 0010001 ..... ..... 000 ..... 1010011 @r
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fsgnjn_d 0010001 ..... ..... 001 ..... 1010011 @r
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fsgnjx_d 0010001 ..... ..... 010 ..... 1010011 @r
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fmin_d 0010101 ..... ..... 000 ..... 1010011 @r
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fmax_d 0010101 ..... ..... 001 ..... 1010011 @r
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fcvt_s_d 0100000 00001 ..... ... ..... 1010011 @r2_rm
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fcvt_d_s 0100001 00000 ..... ... ..... 1010011 @r2_rm
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feq_d 1010001 ..... ..... 010 ..... 1010011 @r
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flt_d 1010001 ..... ..... 001 ..... 1010011 @r
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fle_d 1010001 ..... ..... 000 ..... 1010011 @r
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fclass_d 1110001 00000 ..... 001 ..... 1010011 @r2
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fcvt_w_d 1100001 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_wu_d 1100001 00001 ..... ... ..... 1010011 @r2_rm
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fcvt_d_w 1101001 00000 ..... ... ..... 1010011 @r2_rm
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fcvt_d_wu 1101001 00001 ..... ... ..... 1010011 @r2_rm
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# *** RV64D Standard Extension (in addition to RV32D) ***
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fcvt_l_d 1100001 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_lu_d 1100001 00011 ..... ... ..... 1010011 @r2_rm
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fmv_x_d 1110001 00000 ..... 000 ..... 1010011 @r2
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fcvt_d_l 1101001 00010 ..... ... ..... 1010011 @r2_rm
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fcvt_d_lu 1101001 00011 ..... ... ..... 1010011 @r2_rm
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fmv_d_x 1111001 00000 ..... 000 ..... 1010011 @r2
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# *** RV32H Base Instruction Set ***
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hlv_b 0110000 00000 ..... 100 ..... 1110011 @r2
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hlv_bu 0110000 00001 ..... 100 ..... 1110011 @r2
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hlv_h 0110010 00000 ..... 100 ..... 1110011 @r2
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hlv_hu 0110010 00001 ..... 100 ..... 1110011 @r2
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hlvx_hu 0110010 00011 ..... 100 ..... 1110011 @r2
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hlv_w 0110100 00000 ..... 100 ..... 1110011 @r2
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hlvx_wu 0110100 00011 ..... 100 ..... 1110011 @r2
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hsv_b 0110001 ..... ..... 100 00000 1110011 @r2_s
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hsv_h 0110011 ..... ..... 100 00000 1110011 @r2_s
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hsv_w 0110101 ..... ..... 100 00000 1110011 @r2_s
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hfence_gvma 0110001 ..... ..... 000 00000 1110011 @hfence_gvma
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hfence_vvma 0010001 ..... ..... 000 00000 1110011 @hfence_vvma
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# *** RV64H Base Instruction Set ***
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hlv_wu 0110100 00001 ..... 100 ..... 1110011 @r2
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hlv_d 0110110 00000 ..... 100 ..... 1110011 @r2
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hsv_d 0110111 ..... ..... 100 00000 1110011 @r2_s
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# *** Vector loads and stores are encoded within LOADFP/STORE-FP ***
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# Vector unit-stride load/store insns.
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vle8_v ... 000 . 00000 ..... 000 ..... 0000111 @r2_nfvm
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vle16_v ... 000 . 00000 ..... 101 ..... 0000111 @r2_nfvm
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vle32_v ... 000 . 00000 ..... 110 ..... 0000111 @r2_nfvm
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vle64_v ... 000 . 00000 ..... 111 ..... 0000111 @r2_nfvm
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vse8_v ... 000 . 00000 ..... 000 ..... 0100111 @r2_nfvm
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vse16_v ... 000 . 00000 ..... 101 ..... 0100111 @r2_nfvm
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vse32_v ... 000 . 00000 ..... 110 ..... 0100111 @r2_nfvm
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vse64_v ... 000 . 00000 ..... 111 ..... 0100111 @r2_nfvm
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# Vector unit-stride mask load/store insns.
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vlm_v 000 000 1 01011 ..... 000 ..... 0000111 @r2
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vsm_v 000 000 1 01011 ..... 000 ..... 0100111 @r2
|
|
|
|
# Vector strided insns.
|
|
vlse8_v ... 010 . ..... ..... 000 ..... 0000111 @r_nfvm
|
|
vlse16_v ... 010 . ..... ..... 101 ..... 0000111 @r_nfvm
|
|
vlse32_v ... 010 . ..... ..... 110 ..... 0000111 @r_nfvm
|
|
vlse64_v ... 010 . ..... ..... 111 ..... 0000111 @r_nfvm
|
|
vsse8_v ... 010 . ..... ..... 000 ..... 0100111 @r_nfvm
|
|
vsse16_v ... 010 . ..... ..... 101 ..... 0100111 @r_nfvm
|
|
vsse32_v ... 010 . ..... ..... 110 ..... 0100111 @r_nfvm
|
|
vsse64_v ... 010 . ..... ..... 111 ..... 0100111 @r_nfvm
|
|
|
|
# Vector ordered-indexed and unordered-indexed load insns.
|
|
vlxei8_v ... 0-1 . ..... ..... 000 ..... 0000111 @r_nfvm
|
|
vlxei16_v ... 0-1 . ..... ..... 101 ..... 0000111 @r_nfvm
|
|
vlxei32_v ... 0-1 . ..... ..... 110 ..... 0000111 @r_nfvm
|
|
vlxei64_v ... 0-1 . ..... ..... 111 ..... 0000111 @r_nfvm
|
|
|
|
# Vector ordered-indexed and unordered-indexed store insns.
|
|
vsxei8_v ... 0-1 . ..... ..... 000 ..... 0100111 @r_nfvm
|
|
vsxei16_v ... 0-1 . ..... ..... 101 ..... 0100111 @r_nfvm
|
|
vsxei32_v ... 0-1 . ..... ..... 110 ..... 0100111 @r_nfvm
|
|
vsxei64_v ... 0-1 . ..... ..... 111 ..... 0100111 @r_nfvm
|
|
|
|
# Vector unit-stride fault-only-first load insns.
|
|
vle8ff_v ... 000 . 10000 ..... 000 ..... 0000111 @r2_nfvm
|
|
vle16ff_v ... 000 . 10000 ..... 101 ..... 0000111 @r2_nfvm
|
|
vle32ff_v ... 000 . 10000 ..... 110 ..... 0000111 @r2_nfvm
|
|
vle64ff_v ... 000 . 10000 ..... 111 ..... 0000111 @r2_nfvm
|
|
|
|
# Vector whole register insns
|
|
vl1re8_v 000 000 1 01000 ..... 000 ..... 0000111 @r2
|
|
vl1re16_v 000 000 1 01000 ..... 101 ..... 0000111 @r2
|
|
vl1re32_v 000 000 1 01000 ..... 110 ..... 0000111 @r2
|
|
vl1re64_v 000 000 1 01000 ..... 111 ..... 0000111 @r2
|
|
vl2re8_v 001 000 1 01000 ..... 000 ..... 0000111 @r2
|
|
vl2re16_v 001 000 1 01000 ..... 101 ..... 0000111 @r2
|
|
vl2re32_v 001 000 1 01000 ..... 110 ..... 0000111 @r2
|
|
vl2re64_v 001 000 1 01000 ..... 111 ..... 0000111 @r2
|
|
vl4re8_v 011 000 1 01000 ..... 000 ..... 0000111 @r2
|
|
vl4re16_v 011 000 1 01000 ..... 101 ..... 0000111 @r2
|
|
vl4re32_v 011 000 1 01000 ..... 110 ..... 0000111 @r2
|
|
vl4re64_v 011 000 1 01000 ..... 111 ..... 0000111 @r2
|
|
vl8re8_v 111 000 1 01000 ..... 000 ..... 0000111 @r2
|
|
vl8re16_v 111 000 1 01000 ..... 101 ..... 0000111 @r2
|
|
vl8re32_v 111 000 1 01000 ..... 110 ..... 0000111 @r2
|
|
vl8re64_v 111 000 1 01000 ..... 111 ..... 0000111 @r2
|
|
vs1r_v 000 000 1 01000 ..... 000 ..... 0100111 @r2
|
|
vs2r_v 001 000 1 01000 ..... 000 ..... 0100111 @r2
|
|
vs4r_v 011 000 1 01000 ..... 000 ..... 0100111 @r2
|
|
vs8r_v 111 000 1 01000 ..... 000 ..... 0100111 @r2
|
|
|
|
# *** new major opcode OP-V ***
|
|
vadd_vv 000000 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vadd_vx 000000 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vadd_vi 000000 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsub_vv 000010 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsub_vx 000010 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vrsub_vx 000011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vrsub_vi 000011 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vwaddu_vv 110000 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwaddu_vx 110000 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwadd_vv 110001 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwadd_vx 110001 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwsubu_vv 110010 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwsubu_vx 110010 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwsub_vv 110011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwsub_vx 110011 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwaddu_wv 110100 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwaddu_wx 110100 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwadd_wv 110101 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwadd_wx 110101 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwsubu_wv 110110 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwsubu_wx 110110 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwsub_wv 110111 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwsub_wx 110111 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vadc_vvm 010000 0 ..... ..... 000 ..... 1010111 @r_vm_1
|
|
vadc_vxm 010000 0 ..... ..... 100 ..... 1010111 @r_vm_1
|
|
vadc_vim 010000 0 ..... ..... 011 ..... 1010111 @r_vm_1
|
|
vmadc_vvm 010001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmadc_vxm 010001 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmadc_vim 010001 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsbc_vvm 010010 0 ..... ..... 000 ..... 1010111 @r_vm_1
|
|
vsbc_vxm 010010 0 ..... ..... 100 ..... 1010111 @r_vm_1
|
|
vmsbc_vvm 010011 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmsbc_vxm 010011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vand_vv 001001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vand_vx 001001 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vand_vi 001001 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vor_vv 001010 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vor_vx 001010 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vor_vi 001010 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vxor_vv 001011 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vxor_vx 001011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vxor_vi 001011 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsll_vv 100101 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsll_vx 100101 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vsll_vi 100101 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsrl_vv 101000 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsrl_vx 101000 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vsrl_vi 101000 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsra_vv 101001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsra_vx 101001 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vsra_vi 101001 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vnsrl_wv 101100 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vnsrl_wx 101100 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vnsrl_wi 101100 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vnsra_wv 101101 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vnsra_wx 101101 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vnsra_wi 101101 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmseq_vv 011000 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmseq_vx 011000 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmseq_vi 011000 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmsne_vv 011001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmsne_vx 011001 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsne_vi 011001 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmsltu_vv 011010 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmsltu_vx 011010 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmslt_vv 011011 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmslt_vx 011011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsleu_vv 011100 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmsleu_vx 011100 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsleu_vi 011100 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmsle_vv 011101 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmsle_vx 011101 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsle_vi 011101 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmsgtu_vx 011110 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsgtu_vi 011110 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vmsgt_vx 011111 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmsgt_vi 011111 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vminu_vv 000100 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vminu_vx 000100 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmin_vv 000101 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmin_vx 000101 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmaxu_vv 000110 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmaxu_vx 000110 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmax_vv 000111 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vmax_vx 000111 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vmul_vv 100101 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmul_vx 100101 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmulh_vv 100111 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmulh_vx 100111 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmulu_vv 111000 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmulu_vx 111000 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmulsu_vv 111010 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmulsu_vx 111010 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmul_vv 111011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmul_vx 111011 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmacc_vv 101101 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmacc_vx 101101 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vnmsac_vv 101111 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vnmsac_vx 101111 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmaccsu_vv 111111 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwmaccsu_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vwmaccus_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vmv_v_v 010111 1 00000 ..... 000 ..... 1010111 @r2
|
|
vmv_v_x 010111 1 00000 ..... 100 ..... 1010111 @r2
|
|
vmv_v_i 010111 1 00000 ..... 011 ..... 1010111 @r2
|
|
vmerge_vvm 010111 0 ..... ..... 000 ..... 1010111 @r_vm_0
|
|
vmerge_vxm 010111 0 ..... ..... 100 ..... 1010111 @r_vm_0
|
|
vmerge_vim 010111 0 ..... ..... 011 ..... 1010111 @r_vm_0
|
|
vsaddu_vv 100000 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsaddu_vx 100000 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vsaddu_vi 100000 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vsadd_vv 100001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsadd_vx 100001 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vsadd_vi 100001 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vssubu_vv 100010 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vssubu_vx 100010 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vssub_vv 100011 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vssub_vx 100011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vaadd_vv 001001 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vaadd_vx 001001 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vaaddu_vv 001000 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vaaddu_vx 001000 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vasub_vv 001011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vasub_vx 001011 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vasubu_vv 001010 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vasubu_vx 001010 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vsmul_vv 100111 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vsmul_vx 100111 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vssrl_vv 101010 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vssrl_vx 101010 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vssrl_vi 101010 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vssra_vv 101011 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vssra_vx 101011 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vssra_vi 101011 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vnclipu_wv 101110 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vnclipu_wx 101110 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vnclipu_wi 101110 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vnclip_wv 101111 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vnclip_wx 101111 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vnclip_wi 101111 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vfadd_vv 000000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfadd_vf 000000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfsub_vv 000010 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfsub_vf 000010 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfrsub_vf 100111 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwadd_vv 110000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwadd_vf 110000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwadd_wv 110100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwadd_wf 110100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwsub_vv 110010 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwsub_vf 110010 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwsub_wv 110110 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwsub_wf 110110 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmul_vv 100100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmul_vf 100100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfdiv_vv 100000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfdiv_vf 100000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfrdiv_vf 100001 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwmul_vv 111000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwmul_vf 111000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmacc_vv 101100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfnmacc_vv 101101 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfnmacc_vf 101101 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmacc_vf 101100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmsac_vv 101110 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmsac_vf 101110 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfnmsac_vv 101111 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfnmsac_vf 101111 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmadd_vv 101000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmadd_vf 101000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfnmadd_vv 101001 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfnmadd_vf 101001 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfsqrt_v 010011 . ..... 00000 001 ..... 1010111 @r2_vm
|
|
vfrsqrt7_v 010011 . ..... 00100 001 ..... 1010111 @r2_vm
|
|
vfrec7_v 010011 . ..... 00101 001 ..... 1010111 @r2_vm
|
|
vfmin_vv 000100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmin_vf 000100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfmax_vv 000110 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfmax_vf 000110 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfsgnj_vv 001000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfsgnj_vf 001000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfsgnjn_vv 001001 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfsgnjn_vf 001001 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfsgnjx_vv 001010 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfsgnjx_vf 001010 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfslide1up_vf 001110 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfslide1down_vf 001111 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmfeq_vv 011000 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vmfeq_vf 011000 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmfne_vv 011100 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vmfne_vf 011100 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmflt_vv 011011 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vmflt_vf 011011 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmfle_vv 011001 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vmfle_vf 011001 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmfgt_vf 011101 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vmfge_vf 011111 . ..... ..... 101 ..... 1010111 @r_vm
|
|
vfclass_v 010011 . ..... 10000 001 ..... 1010111 @r2_vm
|
|
vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0
|
|
vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2
|
|
|
|
vfcvt_xu_f_v 010010 . ..... 00000 001 ..... 1010111 @r2_vm
|
|
vfcvt_x_f_v 010010 . ..... 00001 001 ..... 1010111 @r2_vm
|
|
vfcvt_f_xu_v 010010 . ..... 00010 001 ..... 1010111 @r2_vm
|
|
vfcvt_f_x_v 010010 . ..... 00011 001 ..... 1010111 @r2_vm
|
|
vfcvt_rtz_xu_f_v 010010 . ..... 00110 001 ..... 1010111 @r2_vm
|
|
vfcvt_rtz_x_f_v 010010 . ..... 00111 001 ..... 1010111 @r2_vm
|
|
|
|
vfwcvt_xu_f_v 010010 . ..... 01000 001 ..... 1010111 @r2_vm
|
|
vfwcvt_x_f_v 010010 . ..... 01001 001 ..... 1010111 @r2_vm
|
|
vfwcvt_f_xu_v 010010 . ..... 01010 001 ..... 1010111 @r2_vm
|
|
vfwcvt_f_x_v 010010 . ..... 01011 001 ..... 1010111 @r2_vm
|
|
vfwcvt_f_f_v 010010 . ..... 01100 001 ..... 1010111 @r2_vm
|
|
vfwcvt_rtz_xu_f_v 010010 . ..... 01110 001 ..... 1010111 @r2_vm
|
|
vfwcvt_rtz_x_f_v 010010 . ..... 01111 001 ..... 1010111 @r2_vm
|
|
|
|
vfncvt_xu_f_w 010010 . ..... 10000 001 ..... 1010111 @r2_vm
|
|
vfncvt_x_f_w 010010 . ..... 10001 001 ..... 1010111 @r2_vm
|
|
vfncvt_f_xu_w 010010 . ..... 10010 001 ..... 1010111 @r2_vm
|
|
vfncvt_f_x_w 010010 . ..... 10011 001 ..... 1010111 @r2_vm
|
|
vfncvt_f_f_w 010010 . ..... 10100 001 ..... 1010111 @r2_vm
|
|
vfncvt_rod_f_f_w 010010 . ..... 10101 001 ..... 1010111 @r2_vm
|
|
vfncvt_rtz_xu_f_w 010010 . ..... 10110 001 ..... 1010111 @r2_vm
|
|
vfncvt_rtz_x_f_w 010010 . ..... 10111 001 ..... 1010111 @r2_vm
|
|
|
|
vredsum_vs 000000 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredand_vs 000001 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredor_vs 000010 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredxor_vs 000011 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredminu_vs 000100 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredmin_vs 000101 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredmaxu_vs 000110 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vredmax_vs 000111 . ..... ..... 010 ..... 1010111 @r_vm
|
|
vwredsumu_vs 110000 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vwredsum_vs 110001 . ..... ..... 000 ..... 1010111 @r_vm
|
|
# Vector ordered and unordered reduction sum
|
|
vfredusum_vs 000001 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfredosum_vs 000011 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfredmin_vs 000101 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfredmax_vs 000111 . ..... ..... 001 ..... 1010111 @r_vm
|
|
# Vector widening ordered and unordered float reduction sum
|
|
vfwredusum_vs 110001 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vfwredosum_vs 110011 . ..... ..... 001 ..... 1010111 @r_vm
|
|
vmand_mm 011001 - ..... ..... 010 ..... 1010111 @r
|
|
vmnand_mm 011101 - ..... ..... 010 ..... 1010111 @r
|
|
vmandn_mm 011000 - ..... ..... 010 ..... 1010111 @r
|
|
vmxor_mm 011011 - ..... ..... 010 ..... 1010111 @r
|
|
vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r
|
|
vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r
|
|
vmorn_mm 011100 - ..... ..... 010 ..... 1010111 @r
|
|
vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r
|
|
vcpop_m 010000 . ..... 10000 010 ..... 1010111 @r2_vm
|
|
vfirst_m 010000 . ..... 10001 010 ..... 1010111 @r2_vm
|
|
vmsbf_m 010100 . ..... 00001 010 ..... 1010111 @r2_vm
|
|
vmsif_m 010100 . ..... 00011 010 ..... 1010111 @r2_vm
|
|
vmsof_m 010100 . ..... 00010 010 ..... 1010111 @r2_vm
|
|
viota_m 010100 . ..... 10000 010 ..... 1010111 @r2_vm
|
|
vid_v 010100 . 00000 10001 010 ..... 1010111 @r1_vm
|
|
vmv_x_s 010000 1 ..... 00000 010 ..... 1010111 @r2rd
|
|
vmv_s_x 010000 1 00000 ..... 110 ..... 1010111 @r2
|
|
vfmv_f_s 010000 1 ..... 00000 001 ..... 1010111 @r2rd
|
|
vfmv_s_f 010000 1 00000 ..... 101 ..... 1010111 @r2
|
|
vslideup_vx 001110 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vslideup_vi 001110 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vslide1up_vx 001110 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vslidedown_vx 001111 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vslidedown_vi 001111 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vslide1down_vx 001111 . ..... ..... 110 ..... 1010111 @r_vm
|
|
vrgather_vv 001100 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vrgatherei16_vv 001110 . ..... ..... 000 ..... 1010111 @r_vm
|
|
vrgather_vx 001100 . ..... ..... 100 ..... 1010111 @r_vm
|
|
vrgather_vi 001100 . ..... ..... 011 ..... 1010111 @r_vm
|
|
vcompress_vm 010111 - ..... ..... 010 ..... 1010111 @r
|
|
vmv1r_v 100111 1 ..... 00000 011 ..... 1010111 @r2rd
|
|
vmv2r_v 100111 1 ..... 00001 011 ..... 1010111 @r2rd
|
|
vmv4r_v 100111 1 ..... 00011 011 ..... 1010111 @r2rd
|
|
vmv8r_v 100111 1 ..... 00111 011 ..... 1010111 @r2rd
|
|
|
|
# Vector Integer Extension
|
|
vzext_vf2 010010 . ..... 00110 010 ..... 1010111 @r2_vm
|
|
vzext_vf4 010010 . ..... 00100 010 ..... 1010111 @r2_vm
|
|
vzext_vf8 010010 . ..... 00010 010 ..... 1010111 @r2_vm
|
|
vsext_vf2 010010 . ..... 00111 010 ..... 1010111 @r2_vm
|
|
vsext_vf4 010010 . ..... 00101 010 ..... 1010111 @r2_vm
|
|
vsext_vf8 010010 . ..... 00011 010 ..... 1010111 @r2_vm
|
|
|
|
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm11
|
|
vsetivli 11 .......... ..... 111 ..... 1010111 @r2_zimm10
|
|
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r
|
|
|
|
# *** RV32 Zba Standard Extension ***
|
|
sh1add 0010000 .......... 010 ..... 0110011 @r
|
|
sh2add 0010000 .......... 100 ..... 0110011 @r
|
|
sh3add 0010000 .......... 110 ..... 0110011 @r
|
|
|
|
# *** RV64 Zba Standard Extension (in addition to RV32 Zba) ***
|
|
add_uw 0000100 .......... 000 ..... 0111011 @r
|
|
sh1add_uw 0010000 .......... 010 ..... 0111011 @r
|
|
sh2add_uw 0010000 .......... 100 ..... 0111011 @r
|
|
sh3add_uw 0010000 .......... 110 ..... 0111011 @r
|
|
slli_uw 00001 ............ 001 ..... 0011011 @sh
|
|
|
|
# *** RV32 Zbb/Zbkb Standard Extension ***
|
|
andn 0100000 .......... 111 ..... 0110011 @r
|
|
rol 0110000 .......... 001 ..... 0110011 @r
|
|
ror 0110000 .......... 101 ..... 0110011 @r
|
|
rori 01100 ............ 101 ..... 0010011 @sh
|
|
# The encoding for rev8 differs between RV32 and RV64.
|
|
# rev8_32 denotes the RV32 variant.
|
|
rev8_32 011010 011000 ..... 101 ..... 0010011 @r2
|
|
# The encoding for zext.h differs between RV32 and RV64.
|
|
# zext_h_32 denotes the RV32 variant.
|
|
{
|
|
zext_h_32 0000100 00000 ..... 100 ..... 0110011 @r2
|
|
pack 0000100 ..... ..... 100 ..... 0110011 @r
|
|
}
|
|
xnor 0100000 .......... 100 ..... 0110011 @r
|
|
# *** RV32 extra Zbb Standard Extension ***
|
|
clz 011000 000000 ..... 001 ..... 0010011 @r2
|
|
cpop 011000 000010 ..... 001 ..... 0010011 @r2
|
|
ctz 011000 000001 ..... 001 ..... 0010011 @r2
|
|
max 0000101 .......... 110 ..... 0110011 @r
|
|
maxu 0000101 .......... 111 ..... 0110011 @r
|
|
min 0000101 .......... 100 ..... 0110011 @r
|
|
minu 0000101 .......... 101 ..... 0110011 @r
|
|
orc_b 001010 000111 ..... 101 ..... 0010011 @r2
|
|
orn 0100000 .......... 110 ..... 0110011 @r
|
|
sext_b 011000 000100 ..... 001 ..... 0010011 @r2
|
|
sext_h 011000 000101 ..... 001 ..... 0010011 @r2
|
|
# *** RV32 extra Zbkb Standard Extension ***
|
|
brev8 0110100 00111 ..... 101 ..... 0010011 @r2 #grevi
|
|
packh 0000100 .......... 111 ..... 0110011 @r
|
|
unzip 0000100 01111 ..... 101 ..... 0010011 @r2 #unshfl
|
|
zip 0000100 01111 ..... 001 ..... 0010011 @r2 #shfl
|
|
|
|
# *** RV64 Zbb/Zbkb Standard Extension (in addition to RV32 Zbb/Zbkb) ***
|
|
# The encoding for rev8 differs between RV32 and RV64.
|
|
# When executing on RV64, the encoding used in RV32 is an illegal
|
|
# instruction, so we use different handler functions to differentiate.
|
|
rev8_64 011010 111000 ..... 101 ..... 0010011 @r2
|
|
rolw 0110000 .......... 001 ..... 0111011 @r
|
|
roriw 0110000 .......... 101 ..... 0011011 @sh5
|
|
rorw 0110000 .......... 101 ..... 0111011 @r
|
|
# The encoding for zext.h differs between RV32 and RV64.
|
|
# When executing on RV64, the encoding used in RV32 is an illegal
|
|
# instruction, so we use different handler functions to differentiate.
|
|
{
|
|
zext_h_64 0000100 00000 ..... 100 ..... 0111011 @r2
|
|
packw 0000100 ..... ..... 100 ..... 0111011 @r
|
|
}
|
|
# *** RV64 extra Zbb Standard Extension (in addition to RV32 Zbb) ***
|
|
clzw 0110000 00000 ..... 001 ..... 0011011 @r2
|
|
ctzw 0110000 00001 ..... 001 ..... 0011011 @r2
|
|
cpopw 0110000 00010 ..... 001 ..... 0011011 @r2
|
|
|
|
# *** RV32 Zbc/Zbkc Standard Extension ***
|
|
clmul 0000101 .......... 001 ..... 0110011 @r
|
|
clmulh 0000101 .......... 011 ..... 0110011 @r
|
|
# *** RV32 extra Zbc Standard Extension ***
|
|
clmulr 0000101 .......... 010 ..... 0110011 @r
|
|
|
|
# *** RV32 Zbkx Standard Extension ***
|
|
xperm4 0010100 .......... 010 ..... 0110011 @r
|
|
xperm8 0010100 .......... 100 ..... 0110011 @r
|
|
|
|
# *** RV32 Zbs Standard Extension ***
|
|
bclr 0100100 .......... 001 ..... 0110011 @r
|
|
bclri 01001. ........... 001 ..... 0010011 @sh
|
|
bext 0100100 .......... 101 ..... 0110011 @r
|
|
bexti 01001. ........... 101 ..... 0010011 @sh
|
|
binv 0110100 .......... 001 ..... 0110011 @r
|
|
binvi 01101. ........... 001 ..... 0010011 @sh
|
|
bset 0010100 .......... 001 ..... 0110011 @r
|
|
bseti 00101. ........... 001 ..... 0010011 @sh
|
|
|
|
# *** RV32 Zfh Extension ***
|
|
flh ............ ..... 001 ..... 0000111 @i
|
|
fsh ....... ..... ..... 001 ..... 0100111 @s
|
|
fmadd_h ..... 10 ..... ..... ... ..... 1000011 @r4_rm
|
|
fmsub_h ..... 10 ..... ..... ... ..... 1000111 @r4_rm
|
|
fnmsub_h ..... 10 ..... ..... ... ..... 1001011 @r4_rm
|
|
fnmadd_h ..... 10 ..... ..... ... ..... 1001111 @r4_rm
|
|
fadd_h 0000010 ..... ..... ... ..... 1010011 @r_rm
|
|
fsub_h 0000110 ..... ..... ... ..... 1010011 @r_rm
|
|
fmul_h 0001010 ..... ..... ... ..... 1010011 @r_rm
|
|
fdiv_h 0001110 ..... ..... ... ..... 1010011 @r_rm
|
|
fsqrt_h 0101110 00000 ..... ... ..... 1010011 @r2_rm
|
|
fsgnj_h 0010010 ..... ..... 000 ..... 1010011 @r
|
|
fsgnjn_h 0010010 ..... ..... 001 ..... 1010011 @r
|
|
fsgnjx_h 0010010 ..... ..... 010 ..... 1010011 @r
|
|
fmin_h 0010110 ..... ..... 000 ..... 1010011 @r
|
|
fmax_h 0010110 ..... ..... 001 ..... 1010011 @r
|
|
fcvt_h_s 0100010 00000 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_s_h 0100000 00010 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_h_d 0100010 00001 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_d_h 0100001 00010 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_w_h 1100010 00000 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_wu_h 1100010 00001 ..... ... ..... 1010011 @r2_rm
|
|
fmv_x_h 1110010 00000 ..... 000 ..... 1010011 @r2
|
|
feq_h 1010010 ..... ..... 010 ..... 1010011 @r
|
|
flt_h 1010010 ..... ..... 001 ..... 1010011 @r
|
|
fle_h 1010010 ..... ..... 000 ..... 1010011 @r
|
|
fclass_h 1110010 00000 ..... 001 ..... 1010011 @r2
|
|
fcvt_h_w 1101010 00000 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_h_wu 1101010 00001 ..... ... ..... 1010011 @r2_rm
|
|
fmv_h_x 1111010 00000 ..... 000 ..... 1010011 @r2
|
|
|
|
# *** RV64 Zfh Extension (in addition to RV32 Zfh) ***
|
|
fcvt_l_h 1100010 00010 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_lu_h 1100010 00011 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_h_l 1101010 00010 ..... ... ..... 1010011 @r2_rm
|
|
fcvt_h_lu 1101010 00011 ..... ... ..... 1010011 @r2_rm
|
|
|
|
# *** Svinval Standard Extension ***
|
|
sinval_vma 0001011 ..... ..... 000 00000 1110011 @sfence_vma
|
|
sfence_w_inval 0001100 00000 00000 000 00000 1110011
|
|
sfence_inval_ir 0001100 00001 00000 000 00000 1110011
|
|
hinval_vvma 0010011 ..... ..... 000 00000 1110011 @hfence_vvma
|
|
hinval_gvma 0110011 ..... ..... 000 00000 1110011 @hfence_gvma
|
|
|
|
# *** RV32 Zknd Standard Extension ***
|
|
aes32dsmi .. 10111 ..... ..... 000 ..... 0110011 @k_aes
|
|
aes32dsi .. 10101 ..... ..... 000 ..... 0110011 @k_aes
|
|
# *** RV64 Zknd Standard Extension ***
|
|
aes64dsm 00 11111 ..... ..... 000 ..... 0110011 @r
|
|
aes64ds 00 11101 ..... ..... 000 ..... 0110011 @r
|
|
aes64im 00 11000 00000 ..... 001 ..... 0010011 @r2
|
|
# *** RV32 Zkne Standard Extension ***
|
|
aes32esmi .. 10011 ..... ..... 000 ..... 0110011 @k_aes
|
|
aes32esi .. 10001 ..... ..... 000 ..... 0110011 @k_aes
|
|
# *** RV64 Zkne Standard Extension ***
|
|
aes64es 00 11001 ..... ..... 000 ..... 0110011 @r
|
|
aes64esm 00 11011 ..... ..... 000 ..... 0110011 @r
|
|
# *** RV64 Zkne/zknd Standard Extension ***
|
|
aes64ks2 01 11111 ..... ..... 000 ..... 0110011 @r
|
|
aes64ks1i 00 11000 1.... ..... 001 ..... 0010011 @i_aes
|
|
# *** RV32 Zknh Standard Extension ***
|
|
sha256sig0 00 01000 00010 ..... 001 ..... 0010011 @r2
|
|
sha256sig1 00 01000 00011 ..... 001 ..... 0010011 @r2
|
|
sha256sum0 00 01000 00000 ..... 001 ..... 0010011 @r2
|
|
sha256sum1 00 01000 00001 ..... 001 ..... 0010011 @r2
|
|
sha512sum0r 01 01000 ..... ..... 000 ..... 0110011 @r
|
|
sha512sum1r 01 01001 ..... ..... 000 ..... 0110011 @r
|
|
sha512sig0l 01 01010 ..... ..... 000 ..... 0110011 @r
|
|
sha512sig0h 01 01110 ..... ..... 000 ..... 0110011 @r
|
|
sha512sig1l 01 01011 ..... ..... 000 ..... 0110011 @r
|
|
sha512sig1h 01 01111 ..... ..... 000 ..... 0110011 @r
|
|
# *** RV64 Zknh Standard Extension ***
|
|
sha512sig0 00 01000 00110 ..... 001 ..... 0010011 @r2
|
|
sha512sig1 00 01000 00111 ..... 001 ..... 0010011 @r2
|
|
sha512sum0 00 01000 00100 ..... 001 ..... 0010011 @r2
|
|
sha512sum1 00 01000 00101 ..... 001 ..... 0010011 @r2
|
|
# *** RV32 Zksh Standard Extension ***
|
|
sm3p0 00 01000 01000 ..... 001 ..... 0010011 @r2
|
|
sm3p1 00 01000 01001 ..... 001 ..... 0010011 @r2
|
|
# *** RV32 Zksed Standard Extension ***
|
|
sm4ed .. 11000 ..... ..... 000 ..... 0110011 @k_aes
|
|
sm4ks .. 11010 ..... ..... 000 ..... 0110011 @k_aes
|