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167 lines
4.3 KiB
C
167 lines
4.3 KiB
C
/*
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* CXL CDAT Structure
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*
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* Copyright (C) 2021 Avery Design Systems, Inc.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef CXL_CDAT_H
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#define CXL_CDAT_H
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#include "hw/cxl/cxl_pci.h"
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/*
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* Reference:
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* Coherent Device Attribute Table (CDAT) Specification, Rev. 1.03, July. 2022
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* Compute Express Link (CXL) Specification, Rev. 3.0, Aug. 2022
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*/
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/* Table Access DOE - CXL r3.0 8.1.11 */
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#define CXL_DOE_TABLE_ACCESS 2
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#define CXL_DOE_PROTOCOL_CDAT ((CXL_DOE_TABLE_ACCESS << 16) | CXL_VENDOR_ID)
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/* Read Entry - CXL r3.0 8.1.11.1 */
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#define CXL_DOE_TAB_TYPE_CDAT 0
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#define CXL_DOE_TAB_ENT_MAX 0xFFFF
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/* Read Entry Request - CXL r3.0 8.1.11.1 Table 8-13 */
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#define CXL_DOE_TAB_REQ 0
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typedef struct CDATReq {
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DOEHeader header;
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uint8_t req_code;
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uint8_t table_type;
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uint16_t entry_handle;
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} QEMU_PACKED CDATReq;
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/* Read Entry Response - CXL r3.0 8.1.11.1 Table 8-14 */
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#define CXL_DOE_TAB_RSP 0
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typedef struct CDATRsp {
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DOEHeader header;
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uint8_t rsp_code;
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uint8_t table_type;
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uint16_t entry_handle;
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} QEMU_PACKED CDATRsp;
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/* CDAT Table Format - CDAT Table 1 */
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#define CXL_CDAT_REV 2
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typedef struct CDATTableHeader {
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uint32_t length;
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uint8_t revision;
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uint8_t checksum;
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uint8_t reserved[6];
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uint32_t sequence;
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} QEMU_PACKED CDATTableHeader;
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/* CDAT Structure Types - CDAT Table 2 */
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typedef enum {
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CDAT_TYPE_DSMAS = 0,
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CDAT_TYPE_DSLBIS = 1,
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CDAT_TYPE_DSMSCIS = 2,
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CDAT_TYPE_DSIS = 3,
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CDAT_TYPE_DSEMTS = 4,
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CDAT_TYPE_SSLBIS = 5,
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} CDATType;
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typedef struct CDATSubHeader {
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uint8_t type;
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uint8_t reserved;
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uint16_t length;
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} CDATSubHeader;
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/* Device Scoped Memory Affinity Structure - CDAT Table 3 */
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typedef struct CDATDsmas {
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CDATSubHeader header;
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uint8_t DSMADhandle;
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uint8_t flags;
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#define CDAT_DSMAS_FLAG_NV (1 << 2)
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#define CDAT_DSMAS_FLAG_SHAREABLE (1 << 3)
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#define CDAT_DSMAS_FLAG_HW_COHERENT (1 << 4)
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#define CDAT_DSMAS_FLAG_DYNAMIC_CAP (1 << 5)
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uint16_t reserved;
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uint64_t DPA_base;
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uint64_t DPA_length;
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} QEMU_PACKED CDATDsmas;
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/* Device Scoped Latency and Bandwidth Information Structure - CDAT Table 5 */
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typedef struct CDATDslbis {
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CDATSubHeader header;
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uint8_t handle;
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/* Definitions of these fields refer directly to HMAT fields */
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uint8_t flags;
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uint8_t data_type;
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uint8_t reserved;
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uint64_t entry_base_unit;
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uint16_t entry[3];
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uint16_t reserved2;
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} QEMU_PACKED CDATDslbis;
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/* Device Scoped Memory Side Cache Information Structure - CDAT Table 6 */
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typedef struct CDATDsmscis {
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CDATSubHeader header;
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uint8_t DSMAS_handle;
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uint8_t reserved[3];
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uint64_t memory_side_cache_size;
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uint32_t cache_attributes;
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} QEMU_PACKED CDATDsmscis;
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/* Device Scoped Initiator Structure - CDAT Table 7 */
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typedef struct CDATDsis {
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CDATSubHeader header;
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uint8_t flags;
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uint8_t handle;
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uint16_t reserved;
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} QEMU_PACKED CDATDsis;
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/* Device Scoped EFI Memory Type Structure - CDAT Table 8 */
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typedef struct CDATDsemts {
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CDATSubHeader header;
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uint8_t DSMAS_handle;
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uint8_t EFI_memory_type_attr;
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uint16_t reserved;
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uint64_t DPA_offset;
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uint64_t DPA_length;
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} QEMU_PACKED CDATDsemts;
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/* Switch Scoped Latency and Bandwidth Information Structure - CDAT Table 9 */
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typedef struct CDATSslbisHeader {
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CDATSubHeader header;
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uint8_t data_type;
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uint8_t reserved[3];
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uint64_t entry_base_unit;
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} QEMU_PACKED CDATSslbisHeader;
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#define CDAT_PORT_ID_USP 0x100
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/* Switch Scoped Latency and Bandwidth Entry - CDAT Table 10 */
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typedef struct CDATSslbe {
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uint16_t port_x_id;
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uint16_t port_y_id;
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uint16_t latency_bandwidth;
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uint16_t reserved;
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} QEMU_PACKED CDATSslbe;
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typedef struct CDATSslbis {
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CDATSslbisHeader sslbis_header;
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CDATSslbe sslbe[];
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} QEMU_PACKED CDATSslbis;
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typedef struct CDATEntry {
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void *base;
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uint32_t length;
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} CDATEntry;
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typedef struct CDATObject {
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CDATEntry *entry;
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int entry_len;
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int (*build_cdat_table)(CDATSubHeader ***cdat_table, void *priv);
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void (*free_cdat_table)(CDATSubHeader **cdat_table, int num, void *priv);
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bool to_update;
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void *private;
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char *filename;
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uint8_t *buf;
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struct CDATSubHeader **built_buf;
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int built_buf_len;
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} CDATObject;
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#endif /* CXL_CDAT_H */
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