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${ noResults }
Jonathan Cameron
882877fc35
hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE
This Data Object Exchange Mailbox allows software to query the latency and bandwidth between ports on the switch. For now only provide information on routes between the upstream port and each downstream port (not p2p). Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> -- Changes since v8: Mostly to match the type 3 equivalent - Move enum out of function and give it a more descriptive namespace. Message-Id: <20221014151045.24781-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
2 years ago | |
|---|---|---|
| .. | ||
| cxl.h | pci-bridge/cxl_upstream: Add a CXL switch upstream port | 2 years ago |
| cxl_cdat.h | hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE | 2 years ago |
| cxl_component.h | hw/cxl/cdat: CXL CDAT Data Object Exchange implementation | 2 years ago |
| cxl_device.h | hw/cxl/cdat: CXL CDAT Data Object Exchange implementation | 2 years ago |
| cxl_host.h | pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. | 2 years ago |
| cxl_pci.h | hw/cxl/cdat: CXL CDAT Data Object Exchange implementation | 2 years ago |