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fc976a67de
Indirect branches to addresses taken from registers go through address
generation, e.g., for BRANCH ON CONDITION Principles of Operation says:
In the RR format, the contents of general register R2 are used to
generate the branch address
QEMU uses r2_nz handler for the respective register operands. Currently
it does not zero out extra bits in 24- and 31-bit addressing modes as
required by address generation. The very frequently used
s390x_tr_init_disas_context() function has a workaround for this,
but the code for saving an old PSW during an interrupt does not.
Add the missing masking to r2_nz. Enforce PSW validity by replacing the
workaround with an assertion.
Reported-by: Thomas Weißschuh <linux@weissschuh.net>
Reported-by: Heiko Carstens <hca@linux.ibm.com>
Link: https://lore.kernel.org/lkml/ab3131a2-c42a-47ff-bf03-e9f68ac053c0@t-8ch.de/
Cc: qemu-stable@nongnu.org
Signed-off-by: Ilya Leoshkevich <iii@linux.ibm.com>
Tested-by: Thomas Weißschuh <linux@weissschuh.net>
Message-ID: <20251016175954.41153-4-iii@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
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5 days ago | |
|---|---|---|
| .. | ||
| cc_helper.c | 6 months ago | |
| crypto_helper.c | 6 months ago | |
| excp_helper.c | 1 week ago | |
| fpu_helper.c | 6 months ago | |
| insn-data.h.inc | 9 months ago | |
| insn-format.h.inc | 3 years ago | |
| int_helper.c | 6 months ago | |
| mem_helper.c | 5 days ago | |
| meson.build | ||
| misc_helper.c | 5 days ago | |
| s390-tod.h | ||
| tcg_s390x.h | 4 years ago | |
| translate.c | 5 days ago | |
| translate_vx.c.inc | 3 weeks ago | |
| vec.h | 4 years ago | |
| vec_fpu_helper.c | 6 months ago | |
| vec_helper.c | 6 months ago | |
| vec_int_helper.c | 2 years ago | |
| vec_string_helper.c | 2 years ago | |