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622 lines
16 KiB
Plaintext
622 lines
16 KiB
Plaintext
#
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# Renesas RX instruction decode definitions.
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#
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# Copyright (c) 2019 Richard Henderson <richard.henderson@linaro.org>
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# Copyright (c) 2019 Yoshinori Sato <ysato@users.sourceforge.jp>
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#
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# This library is free software; you can redistribute it and/or
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# modify it under the terms of the GNU Lesser General Public
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# License as published by the Free Software Foundation; either
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# version 2.1 of the License, or (at your option) any later version.
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#
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# This library is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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# Lesser General Public License for more details.
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#
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# You should have received a copy of the GNU Lesser General Public
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# License along with this library; if not, see <http://www.gnu.org/licenses/>.
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#
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&bcnd cd dsp sz
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&jdsp dsp sz
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&jreg rs
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&rr rd rs
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&ri rd imm
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&rrr rd rs rs2
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&rri rd imm rs2
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&rm rd rs ld mi
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&mi rs ld mi imm
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&mr rs ld mi rs2
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&mcnd ld sz rd cd
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########
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%b1_bdsp 24:3 !function=bdsp_s
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@b1_bcnd_s .... cd:1 ... &bcnd dsp=%b1_bdsp sz=1
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@b1_bra_s .... .... &jdsp dsp=%b1_bdsp sz=1
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%b2_r_0 16:4
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%b2_li_2 18:2 !function=li
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%b2_li_8 24:2 !function=li
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%b2_dsp5_3 23:4 19:1
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@b2_rds .... .... .... rd:4 &rr rs=%b2_r_0
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@b2_rds_li .... .... .... rd:4 &rri rs2=%b2_r_0 imm=%b2_li_8
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@b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=%b2_r_0
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@b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=0
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@b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=%b2_r_0
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@b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=%b2_li_8
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@b2_rd_ld_ub .... .. ld:2 rs:4 rd:4 &rm mi=4
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@b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=4
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@b2_bcnd_b .... cd:4 dsp:s8 &bcnd sz=2
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@b2_bra_b .... .... dsp:s8 &jdsp sz=2
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########
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%b3_r_0 8:4
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%b3_li_10 18:2 !function=li
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%b3_dsp5_8 23:1 16:4
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%b3_bdsp 8:s8 16:8
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@b3_rd_rs .... .... .... .... rs:4 rd:4 &rr
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@b3_rs_rd .... .... .... .... rd:4 rs:4 &rr
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@b3_rd_li .... .... .... .... .... rd:4 \
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&rri rs2=%b3_r_0 imm=%b3_li_10
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@b3_rd_ld .... .... mi:2 .... ld:2 rs:4 rd:4 &rm
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@b3_rd_ld_ub .... .... .... .. ld:2 rs:4 rd:4 &rm mi=4
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@b3_rd_ld_ul .... .... .... .. ld:2 rs:4 rd:4 &rm mi=2
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@b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr
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@b3_rds_imm5 .... .... ....... imm:5 rd:4 &rri rs2=%b3_r_0
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@b3_rd_rs_imm5 .... .... ... imm:5 rs2:4 rd:4 &rri
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@b3_bcnd_w .... ... cd:1 .... .... .... .... &bcnd dsp=%b3_bdsp sz=3
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@b3_bra_w .... .... .... .... .... .... &jdsp dsp=%b3_bdsp sz=3
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@b3_ld_rd_rs .... .... .... .. ld:2 rs:4 rd:4 &rm mi=0
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@b3_sz_ld_rd_cd .... .... .... sz:2 ld:2 rd:4 cd:4 &mcnd
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########
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%b4_li_18 18:2 !function=li
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%b4_dsp_16 0:s8 8:8
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%b4_bdsp 0:s8 8:8 16:8
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@b4_rd_ldmi .... .... mi:2 .... ld:2 .... .... rs:4 rd:4 &rm
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@b4_bra_a .... .... .... .... .... .... .... .... \
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&jdsp dsp=%b4_bdsp sz=4
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########
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# ABS rd
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ABS_rr 0111 1110 0010 .... @b2_rds
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# ABS rs, rd
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ABS_rr 1111 1100 0000 1111 .... .... @b3_rd_rs
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# ADC #imm, rd
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ADC_ir 1111 1101 0111 ..00 0010 .... @b3_rd_li
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# ADC rs, rd
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ADC_rr 1111 1100 0000 1011 .... .... @b3_rd_rs
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# ADC dsp[rs].l, rd
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# Note only mi==2 allowed.
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ADC_mr 0000 0110 ..10 00.. 0000 0010 .... .... @b4_rd_ldmi
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# ADD #uimm4, rd
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ADD_irr 0110 0010 .... .... @b2_rds_uimm4
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# ADD #imm, rs, rd
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ADD_irr 0111 00.. .... .... @b2_rd_rs_li
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# ADD dsp[rs].ub, rd
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# ADD rs, rd
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ADD_mr 0100 10.. .... .... @b2_rd_ld_ub
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# ADD dsp[rs], rd
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ADD_mr 0000 0110 ..00 10.. .... .... @b3_rd_ld
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# ADD rs, rs2, rd
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ADD_rrr 1111 1111 0010 .... .... .... @b3_rd_rs_rs2
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# AND #uimm4, rd
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AND_ir 0110 0100 .... .... @b2_rds_uimm4
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# AND #imm, rd
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AND_ir 0111 01.. 0010 .... @b2_rds_li
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# AND dsp[rs].ub, rd
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# AND rs, rd
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AND_mr 0101 00.. .... .... @b2_rd_ld_ub
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# AND dsp[rs], rd
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AND_mr 0000 0110 ..01 00.. .... .... @b3_rd_ld
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# AND rs, rs2, rd
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AND_rrr 1111 1111 0100 .... .... .... @b3_rd_rs_rs2
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# BCLR #imm, dsp[rd]
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BCLR_im 1111 00.. .... 1... @b2_ld_imm3
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# BCLR #imm, rs
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BCLR_ir 0111 101. .... .... @b2_rds_imm5
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# BCLR rs, rd
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# BCLR rs, dsp[rd]
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{
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BCLR_rr 1111 1100 0110 0111 .... .... @b3_rs_rd
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BCLR_rm 1111 1100 0110 01.. .... .... @b3_rd_ld_ub
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}
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# BCnd.s dsp
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BCnd 0001 .... @b1_bcnd_s
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# BRA.b dsp
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# BCnd.b dsp
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{
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BRA 0010 1110 .... .... @b2_bra_b
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BCnd 0010 .... .... .... @b2_bcnd_b
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}
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# BCnd.w dsp
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BCnd 0011 101 . .... .... .... .... @b3_bcnd_w
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# BNOT #imm, dsp[rd]
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# BMCnd #imm, dsp[rd]
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{
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BNOT_im 1111 1100 111 imm:3 ld:2 rs:4 1111
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BMCnd_im 1111 1100 111 imm:3 ld:2 rd:4 cd:4
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}
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# BNOT #imm, rd
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# BMCnd #imm, rd
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{
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BNOT_ir 1111 1101 111 imm:5 1111 rd:4
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BMCnd_ir 1111 1101 111 imm:5 cd:4 rd:4
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}
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# BNOT rs, rd
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# BNOT rs, dsp[rd]
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{
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BNOT_rr 1111 1100 0110 1111 .... .... @b3_rs_rd
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BNOT_rm 1111 1100 0110 11.. .... .... @b3_rd_ld_ub
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}
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# BRA.s dsp
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BRA 0000 1 ... @b1_bra_s
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# BRA.w dsp
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BRA 0011 1000 .... .... .... .... @b3_bra_w
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# BRA.a dsp
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BRA 0000 0100 .... .... .... .... .... .... @b4_bra_a
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# BRA.l rs
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BRA_l 0111 1111 0100 rd:4
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BRK 0000 0000
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# BSET #imm, dsp[rd]
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BSET_im 1111 00.. .... 0... @b2_ld_imm3
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# BSET #imm, rd
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BSET_ir 0111 100. .... .... @b2_rds_imm5
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# BSET rs, rd
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# BSET rs, dsp[rd]
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{
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BSET_rr 1111 1100 0110 0011 .... .... @b3_rs_rd
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BSET_rm 1111 1100 0110 00.. .... .... @b3_rd_ld_ub
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}
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# BSR.w dsp
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BSR 0011 1001 .... .... .... .... @b3_bra_w
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# BSR.a dsp
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BSR 0000 0101 .... .... .... .... .... .... @b4_bra_a
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# BSR.l rs
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BSR_l 0111 1111 0101 rd:4
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# BSET #imm, dsp[rd]
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BTST_im 1111 01.. .... 0... @b2_ld_imm3
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# BSET #imm, rd
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BTST_ir 0111 110. .... .... @b2_rds_imm5
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# BSET rs, rd
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# BSET rs, dsp[rd]
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{
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BTST_rr 1111 1100 0110 1011 .... .... @b3_rs_rd
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BTST_rm 1111 1100 0110 10.. .... .... @b3_rd_ld_ub
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}
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# CLRSPW psw
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CLRPSW 0111 1111 1011 cb:4
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# CMP #uimm4, rs2
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CMP_ir 0110 0001 .... .... @b2_rs2_uimm4
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# CMP #uimm8, rs2
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CMP_ir 0111 0101 0101 rs2:4 imm:8 &rri rd=0
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# CMP #imm, rs2
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CMP_ir 0111 01.. 0000 rs2:4 &rri imm=%b2_li_8 rd=0
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# CMP dsp[rs].ub, rs2
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# CMP rs, rs2
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CMP_mr 0100 01.. .... .... @b2_rd_ld_ub
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# CMP dsp[rs], rs2
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CMP_mr 0000 0110 ..00 01.. .... .... @b3_rd_ld
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# DIV #imm, rd
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DIV_ir 1111 1101 0111 ..00 1000 .... @b3_rd_li
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# DIV dsp[rs].ub, rd
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# DIV rs, rd
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DIV_mr 1111 1100 0010 00.. .... .... @b3_rd_ld_ub
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# DIV dsp[rs], rd
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DIV_mr 0000 0110 ..10 00.. 0000 1000 .... .... @b4_rd_ldmi
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# DIVU #imm, rd
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DIVU_ir 1111 1101 0111 ..00 1001 .... @b3_rd_li
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# DIVU dsp[rs].ub, rd
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# DIVU rs, rd
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DIVU_mr 1111 1100 0010 01.. .... .... @b3_rd_ld_ub
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# DIVU dsp[rs], rd
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DIVU_mr 0000 0110 ..10 00.. 0000 1001 .... .... @b4_rd_ldmi
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# EMUL #imm, rd
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EMUL_ir 1111 1101 0111 ..00 0110 .... @b3_rd_li
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# EMUL dsp[rs].ub, rd
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# EMUL rs, rd
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EMUL_mr 1111 1100 0001 10.. .... .... @b3_rd_ld_ub
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# EMUL dsp[rs], rd
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EMUL_mr 0000 0110 ..10 00.. 0000 0110 .... .... @b4_rd_ldmi
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# EMULU #imm, rd
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EMULU_ir 1111 1101 0111 ..00 0111 .... @b3_rd_li
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# EMULU dsp[rs].ub, rd
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# EMULU rs, rd
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EMULU_mr 1111 1100 0001 11.. .... .... @b3_rd_ld_ub
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# EMULU dsp[rs], rd
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EMULU_mr 0000 0110 ..10 00.. 0000 0111 .... .... @b4_rd_ldmi
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# FADD #imm, rd
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FADD_ir 1111 1101 0111 0010 0010 rd:4
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# FADD rs, rd
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# FADD dsp[rs], rd
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FADD_mr 1111 1100 1000 10.. .... .... @b3_rd_ld_ul
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# FCMP #imm, rd
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FCMP_ir 1111 1101 0111 0010 0001 rd:4
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# FCMP rs, rd
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# FCMP dsp[rs], rd
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FCMP_mr 1111 1100 1000 01.. .... .... @b3_rd_ld_ul
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# FDIV #imm, rd
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FDIV_ir 1111 1101 0111 0010 0100 rd:4
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# FDIV rs, rd
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# FDIV dsp[rs], rd
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FDIV_mr 1111 1100 1001 00.. .... .... @b3_rd_ld_ul
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# FMUL #imm, rd
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FMUL_ir 1111 1101 0111 0010 0011 rd:4
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# FMUL rs, rd
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# FMUL dsp[rs], rd
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FMUL_mr 1111 1100 1000 11.. .... .... @b3_rd_ld_ul
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# FSUB #imm, rd
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FSUB_ir 1111 1101 0111 0010 0000 rd:4
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# FSUB rs, rd
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# FSUB dsp[rs], rd
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FSUB_mr 1111 1100 1000 00.. .... .... @b3_rd_ld_ul
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# FTOI rs, rd
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# FTOI dsp[rs], rd
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FTOI 1111 1100 1001 01.. .... .... @b3_rd_ld_ul
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# INT #uimm8
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INT 0111 0101 0110 0000 imm:8
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# ITOF dsp[rs].ub, rd
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# ITOF rs, rd
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ITOF 1111 1100 0100 01.. .... .... @b3_rd_ld_ub
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# ITOF dsp[rs], rd
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ITOF 0000 0110 ..10 00.. 0001 0001 .... .... @b4_rd_ldmi
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# JMP rs
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JMP 0111 1111 0000 rs:4 &jreg
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# JSR rs
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JSR 0111 1111 0001 rs:4 &jreg
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# MACHI rs, rs2
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MACHI 1111 1101 0000 0100 rs:4 rs2:4
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# MACLO rs, rs2
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MACLO 1111 1101 0000 0101 rs:4 rs2:4
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# MAX #imm, rd
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MAX_ir 1111 1101 0111 ..00 0100 .... @b3_rd_li
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# MAX dsp[rs].ub, rd
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# MAX rs, rd
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MAX_mr 1111 1100 0001 00.. .... .... @b3_rd_ld_ub
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# MAX dsp[rs], rd
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MAX_mr 0000 0110 ..10 00.. 0000 0100 .... .... @b4_rd_ldmi
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# MIN #imm, rd
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MIN_ir 1111 1101 0111 ..00 0101 .... @b3_rd_li
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# MIN dsp[rs].ub, rd
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# MIN rs, rd
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MIN_mr 1111 1100 0001 01.. .... .... @b3_rd_ld_ub
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# MIN dsp[rs], rd
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MIN_mr 0000 0110 ..10 00.. 0000 0101 .... .... @b4_rd_ldmi
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# MOV.b rs, dsp5[rd]
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MOV_rm 1000 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=0
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# MOV.w rs, dsp5[rd]
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MOV_rm 1001 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=1
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# MOV.l rs, dsp5[rd]
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MOV_rm 1010 0 .... rd:3 . rs:3 dsp=%b2_dsp5_3 sz=2
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# MOV.b dsp5[rs], rd
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MOV_mr 1000 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=0
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# MOV.w dsp5[rs], rd
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MOV_mr 1001 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=1
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# MOV.l dsp5[rs], rd
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MOV_mr 1010 1 .... rs:3 . rd:3 dsp=%b2_dsp5_3 sz=2
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# MOV.l #uimm4, rd
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MOV_ir 0110 0110 imm:4 rd:4
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# MOV.b #imm8, dsp5[rd]
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MOV_im 0011 1100 . rd:3 .... imm:8 sz=0 dsp=%b3_dsp5_8
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# MOV.w #imm8, dsp5[rd]
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MOV_im 0011 1101 . rd:3 .... imm:8 sz=1 dsp=%b3_dsp5_8
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# MOV.l #imm8, dsp5[rd]
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MOV_im 0011 1110 . rd:3 .... imm:8 sz=2 dsp=%b3_dsp5_8
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# MOV.l #imm8, rd
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MOV_ir 0111 0101 0100 rd:4 imm:8
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# MOV.l #mm8, rd
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MOV_ir 1111 1011 rd:4 .. 10 imm=%b2_li_2
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# MOV.<bwl> #imm, [rd]
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MOV_im 1111 1000 rd:4 .. sz:2 dsp=0 imm=%b2_li_2
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# MOV.<bwl> #imm, dsp8[rd]
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MOV_im 1111 1001 rd:4 .. sz:2 dsp:8 imm=%b3_li_10
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# MOV.<bwl> #imm, dsp16[rd]
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MOV_im 1111 1010 rd:4 .. sz:2 .... .... .... .... \
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imm=%b4_li_18 dsp=%b4_dsp_16
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# MOV.<bwl> [ri,rb], rd
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MOV_ar 1111 1110 01 sz:2 ri:4 rb:4 rd:4
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# MOV.<bwl> rs, [ri,rb]
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MOV_ra 1111 1110 00 sz:2 ri:4 rb:4 rs:4
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# Note ldd=3 and lds=3 indicate register src or dst
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# MOV.b rs, rd
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# MOV.b rs, dsp[rd]
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# MOV.b dsp[rs], rd
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# MOV.b dsp[rs], dsp[rd]
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MOV_mm 1100 ldd:2 lds:2 rs:4 rd:4 sz=0
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# MOV.w rs, rd
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# MOV.w rs, dsp[rd]
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# MOV.w dsp[rs], rd
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# MOV.w dsp[rs], dsp[rd]
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MOV_mm 1101 ldd:2 lds:2 rs:4 rd:4 sz=1
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# MOV.l rs, rd
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# MOV.l rs, dsp[rd]
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# MOV.l dsp[rs], rd
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# MOV.l dsp[rs], dsp[rd]
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MOV_mm 1110 ldd:2 lds:2 rs:4 rd:4 sz=2
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# MOV.l rs, [rd+]
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# MOV.l rs, [-rd]
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MOV_rp 1111 1101 0010 0 ad:1 sz:2 rd:4 rs:4
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# MOV.l [rs+], rd
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# MOV.l [-rs], rd
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MOV_pr 1111 1101 0010 1 ad:1 sz:2 rd:4 rs:4
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# MOVU.<bw> dsp5[rs], rd
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MOVU_mr 1011 sz:1 ... . rs:3 . rd:3 dsp=%b2_dsp5_3
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# MOVU.<bw> [rs], rd
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MOVU_mr 0101 1 sz:1 00 rs:4 rd:4 dsp=0
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# MOVU.<bw> dsp8[rs], rd
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MOVU_mr 0101 1 sz:1 01 rs:4 rd:4 dsp:8
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# MOVU.<bw> dsp16[rs], rd
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MOVU_mr 0101 1 sz:1 10 rs:4 rd:4 .... .... .... .... dsp=%b4_dsp_16
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# MOVU.<bw> rs, rd
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MOVU_rr 0101 1 sz:1 11 rs:4 rd:4
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# MOVU.<bw> [ri, rb], rd
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MOVU_ar 1111 1110 110 sz:1 ri:4 rb:4 rd:4
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# MOVU.<bw> [rs+], rd
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MOVU_pr 1111 1101 0011 1 ad:1 0 sz:1 rd:4 rs:4
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# MUL #uimm4, rd
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MUL_ir 0110 0011 .... .... @b2_rds_uimm4
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# MUL #imm4, rd
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MUL_ir 0111 01.. 0001 .... @b2_rds_li
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# MUL dsp[rs].ub, rd
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# MUL rs, rd
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MUL_mr 0100 11.. .... .... @b2_rd_ld_ub
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# MUL dsp[rs], rd
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MUL_mr 0000 0110 ..00 11.. .... .... @b3_rd_ld
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# MOV rs, rs2, rd
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MUL_rrr 1111 1111 0011 .... .... .... @b3_rd_rs_rs2
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# MULHI rs, rs2
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MULHI 1111 1101 0000 0000 rs:4 rs2:4
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# MULLO rs, rs2
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MULLO 1111 1101 0000 0001 rs:4 rs2:4
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# MVFACHI rd
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MVFACHI 1111 1101 0001 1111 0000 rd:4
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# MVFACMI rd
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MVFACMI 1111 1101 0001 1111 0010 rd:4
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# MVFC cr, rd
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MVFC 1111 1101 0110 1010 cr:4 rd:4
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# MVTACHI rs
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MVTACHI 1111 1101 0001 0111 0000 rs:4
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# MVTACLO rs
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MVTACLO 1111 1101 0001 0111 0001 rs:4
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|
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# MVTC #imm, cr
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MVTC_i 1111 1101 0111 ..11 0000 cr:4 imm=%b3_li_10
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# MVTC rs, cr
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MVTC_r 1111 1101 0110 1000 rs:4 cr:4
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# MVTIPL #imm
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MVTIPL 0111 0101 0111 0000 0000 imm:4
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# NEG rd
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NEG_rr 0111 1110 0001 .... @b2_rds
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# NEG rs, rd
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NEG_rr 1111 1100 0000 0111 .... .... @b3_rd_rs
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|
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NOP 0000 0011
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# NOT rd
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NOT_rr 0111 1110 0000 .... @b2_rds
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# NOT rs, rd
|
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NOT_rr 1111 1100 0011 1011 .... .... @b3_rd_rs
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|
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# OR #uimm4, rd
|
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OR_ir 0110 0101 .... .... @b2_rds_uimm4
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# OR #imm, rd
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OR_ir 0111 01.. 0011 .... @b2_rds_li
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# OR dsp[rs].ub, rd
|
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# OR rs, rd
|
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OR_mr 0101 01.. .... .... @b2_rd_ld_ub
|
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# OR dsp[rs], rd
|
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OR_mr 0000 0110 .. 0101 .. .... .... @b3_rd_ld
|
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# OR rs, rs2, rd
|
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OR_rrr 1111 1111 0101 .... .... .... @b3_rd_rs_rs2
|
|
|
|
# POP cr
|
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POPC 0111 1110 1110 cr:4
|
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# POP rd-rd2
|
|
POPM 0110 1111 rd:4 rd2:4
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|
|
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# POP rd
|
|
# PUSH.<bwl> rs
|
|
{
|
|
POP 0111 1110 1011 rd:4
|
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PUSH_r 0111 1110 10 sz:2 rs:4
|
|
}
|
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# PUSH.<bwl> dsp[rs]
|
|
PUSH_m 1111 01 ld:2 rs:4 10 sz:2
|
|
# PUSH cr
|
|
PUSHC 0111 1110 1100 cr:4
|
|
# PUSHM rs-rs2
|
|
PUSHM 0110 1110 rs:4 rs2:4
|
|
|
|
# RACW #imm
|
|
RACW 1111 1101 0001 1000 000 imm:1 0000
|
|
|
|
# REVL rs,rd
|
|
REVL 1111 1101 0110 0111 .... .... @b3_rd_rs
|
|
# REVW rs,rd
|
|
REVW 1111 1101 0110 0101 .... .... @b3_rd_rs
|
|
|
|
# SMOVF
|
|
# RPMA.<bwl>
|
|
{
|
|
SMOVF 0111 1111 1000 1111
|
|
RMPA 0111 1111 1000 11 sz:2
|
|
}
|
|
|
|
# ROLC rd
|
|
ROLC 0111 1110 0101 .... @b2_rds
|
|
# RORC rd
|
|
RORC 0111 1110 0100 .... @b2_rds
|
|
|
|
# ROTL #imm, rd
|
|
ROTL_ir 1111 1101 0110 111. .... .... @b3_rds_imm5
|
|
# ROTL rs, rd
|
|
ROTL_rr 1111 1101 0110 0110 .... .... @b3_rd_rs
|
|
|
|
# ROTR #imm, rd
|
|
ROTR_ir 1111 1101 0110 110. .... .... @b3_rds_imm5
|
|
# ROTR #imm, rd
|
|
ROTR_rr 1111 1101 0110 0100 .... .... @b3_rd_rs
|
|
|
|
# ROUND rs,rd
|
|
# ROUND dsp[rs],rd
|
|
ROUND 1111 1100 1001 10 .. .... .... @b3_ld_rd_rs
|
|
|
|
RTE 0111 1111 1001 0101
|
|
|
|
RTFI 0111 1111 1001 0100
|
|
|
|
RTS 0000 0010
|
|
|
|
# RTSD #imm
|
|
RTSD_i 0110 0111 imm:8
|
|
# RTSD #imm, rd-rd2
|
|
RTSD_irr 0011 1111 rd:4 rd2:4 imm:8
|
|
|
|
# SAT rd
|
|
SAT 0111 1110 0011 .... @b2_rds
|
|
# SATR
|
|
SATR 0111 1111 1001 0011
|
|
|
|
# SBB rs, rd
|
|
SBB_rr 1111 1100 0000 0011 .... .... @b3_rd_rs
|
|
# SBB dsp[rs].l, rd
|
|
# Note only mi==2 allowed.
|
|
SBB_mr 0000 0110 ..10 00.. 0000 0000 .... .... @b4_rd_ldmi
|
|
|
|
# SCCnd dsp[rd]
|
|
# SCCnd rd
|
|
SCCnd 1111 1100 1101 .... .... .... @b3_sz_ld_rd_cd
|
|
|
|
# SETPSW psw
|
|
SETPSW 0111 1111 1010 cb:4
|
|
|
|
# SHAR #imm, rd
|
|
SHAR_irr 0110 101. .... .... @b2_rds_imm5
|
|
# SHAR #imm, rs, rd
|
|
SHAR_irr 1111 1101 101. .... .... .... @b3_rd_rs_imm5
|
|
# SHAR rs, rd
|
|
SHAR_rr 1111 1101 0110 0001 .... .... @b3_rd_rs
|
|
|
|
# SHLL #imm, rd
|
|
SHLL_irr 0110 110. .... .... @b2_rds_imm5
|
|
# SHLL #imm, rs, rd
|
|
SHLL_irr 1111 1101 110. .... .... .... @b3_rd_rs_imm5
|
|
# SHLL rs, rd
|
|
SHLL_rr 1111 1101 0110 0010 .... .... @b3_rd_rs
|
|
|
|
# SHLR #imm, rd
|
|
SHLR_irr 0110 100. .... .... @b2_rds_imm5
|
|
# SHLR #imm, rs, rd
|
|
SHLR_irr 1111 1101 100. .... .... .... @b3_rd_rs_imm5
|
|
# SHLR rs, rd
|
|
SHLR_rr 1111 1101 0110 0000 .... .... @b3_rd_rs
|
|
|
|
# SMOVB
|
|
# SSTR.<bwl>
|
|
{
|
|
SMOVB 0111 1111 1000 1011
|
|
SSTR 0111 1111 1000 10 sz:2
|
|
}
|
|
|
|
# STNZ #imm, rd
|
|
STNZ 1111 1101 0111 ..00 1111 .... @b3_rd_li
|
|
# STZ #imm, rd
|
|
STZ 1111 1101 0111 ..00 1110 .... @b3_rd_li
|
|
|
|
# SUB #uimm4, rd
|
|
SUB_ir 0110 0000 .... .... @b2_rds_uimm4
|
|
# SUB dsp[rs].ub, rd
|
|
# SUB rs, rd
|
|
SUB_mr 0100 00.. .... .... @b2_rd_ld_ub
|
|
# SUB dsp[rs], rd
|
|
SUB_mr 0000 0110 ..00 00.. .... .... @b3_rd_ld
|
|
# SUB rs, rs2, rd
|
|
SUB_rrr 1111 1111 0000 .... .... .... @b3_rd_rs_rs2
|
|
|
|
# SCMPU
|
|
# SUNTIL.<bwl>
|
|
{
|
|
SCMPU 0111 1111 1000 0011
|
|
SUNTIL 0111 1111 1000 00 sz:2
|
|
}
|
|
|
|
# SMOVU
|
|
# SWHILE.<bwl>
|
|
{
|
|
SMOVU 0111 1111 1000 0111
|
|
SWHILE 0111 1111 1000 01 sz:2
|
|
}
|
|
|
|
# TST #imm, rd
|
|
TST_ir 1111 1101 0111 ..00 1100 .... @b3_rd_li
|
|
# TST dsp[rs].ub, rd
|
|
# TST rs, rd
|
|
TST_mr 1111 1100 0011 00.. .... .... @b3_rd_ld_ub
|
|
# TST dsp[rs], rd
|
|
TST_mr 0000 0110 ..10 00.. 0000 1100 .... .... @b4_rd_ldmi
|
|
|
|
WAIT 0111 1111 1001 0110
|
|
|
|
# XCHG rs, rd
|
|
# XCHG dsp[rs].ub, rd
|
|
{
|
|
XCHG_rr 1111 1100 0100 0011 .... .... @b3_rd_rs
|
|
XCHG_mr 1111 1100 0100 00.. .... .... @b3_rd_ld_ub
|
|
}
|
|
# XCHG dsp[rs], rd
|
|
XCHG_mr 0000 0110 ..10 00.. 0001 0000 .... .... @b4_rd_ldmi
|
|
|
|
# XOR #imm, rd
|
|
XOR_ir 1111 1101 0111 ..00 1101 .... @b3_rd_li
|
|
# XOR dsp[rs].ub, rd
|
|
# XOR rs, rd
|
|
XOR_mr 1111 1100 0011 01.. .... .... @b3_rd_ld_ub
|
|
# XOR dsp[rs], rd
|
|
XOR_mr 0000 0110 ..10 00.. 0000 1101 .... .... @b4_rd_ldmi
|