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qemu/target/loongarch/tcg/insn_trans
History
Bibo Mao 5cba5a518b target/loongarch: Add CSR_PWCH write helper function 
Bit HPTW_EN in register CSR_PWCH controls enabling hardware page
table walker feature when PTW feature is enabled. Otherwise it is
reserved bit.

Here add register CSR_PWCH write helper function.

Signed-off-by: Bibo Mao <maobibo@loongson.cn>
Reviewed-by: Song Gao <gaosong@loongson.cn>
 		2 weeks ago
..
trans_arith.c.inc
…
trans_atomic.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_bit.c.inc
…
trans_branch.c.inc target/loongarch: Guard BCEQZ/BCNEZ instructions with FP feature 7 months ago
trans_extra.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_farith.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_fcmp.c.inc target/loongarch: add check for fcond 5 months ago
trans_fcnv.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_fmemory.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_fmov.c.inc
…
trans_memory.c.inc
…
trans_privileged.c.inc target/loongarch: Add CSR_PWCH write helper function 2 weeks ago
trans_shift.c.inc target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2 months ago
trans_vec.c.inc target/loongarch: Fix [X]VLDI raising exception incorrectly 3 months ago