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qemu/target/loongarch/tcg/insn_trans
WANG Rui 875caabdb1 target/loongarch: Guard BCEQZ/BCNEZ instructions with FP feature
The BCEQZ and BCNEZ instructions depend on access to condition codes
from floating-point comparisons. Previously, these instructions were
unconditionally enabled for 64-bit targets.

This patch updates their translation to be gated under the `FP` feature
flag instead, ensuring they are only available when the floating-point
unit is present.

This improves correctness for CPUs lacking floating-point support.

Signed-off-by: WANG Rui <wangrui@loongson.cn>
Reviewed-by: Bibo Mao <maobibo@loongson.cn>
Message-Id: <20250418082103.447780-3-wangrui@loongson.cn>
Signed-off-by: Song Gao <gaosong@loongson.cn>
3 days ago
..
trans_arith.c.inc
trans_atomic.c.inc target/loongarch: Use VADDR_PRIx for logging pc_next 2 months ago
trans_bit.c.inc
trans_branch.c.inc target/loongarch: Guard BCEQZ/BCNEZ instructions with FP feature 3 days ago
trans_extra.c.inc target/loongarch: Add CRC feature flag and use it to gate CRC instructions 3 days ago
trans_farith.c.inc
trans_fcmp.c.inc
trans_fcnv.c.inc
trans_fmemory.c.inc
trans_fmov.c.inc
trans_memory.c.inc
trans_privileged.c.inc target/loongarch: check tlb_ps 2 months ago
trans_shift.c.inc target/loongarch: Remove avail_64 in trans_srai_w() and simplify it 10 months ago
trans_vec.c.inc target/loongarch: Use actual operand size with vbsrl check 4 months ago