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573 lines
20 KiB
C
573 lines
20 KiB
C
/*
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* i386 CPU dump to FILE
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "qemu/qemu-print.h"
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#ifndef CONFIG_USER_ONLY
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#include "hw/i386/apic_internal.h"
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#endif
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/***********************************************************/
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/* x86 debug */
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static const char * const cc_op_str[] = {
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[CC_OP_DYNAMIC] = "DYNAMIC",
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[CC_OP_EFLAGS] = "EFLAGS",
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[CC_OP_ADCX] = "ADCX",
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[CC_OP_ADOX] = "ADOX",
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[CC_OP_ADCOX] = "ADCOX",
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[CC_OP_MULB] = "MULB",
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[CC_OP_MULW] = "MULW",
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[CC_OP_MULL] = "MULL",
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[CC_OP_MULQ] = "MULQ",
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[CC_OP_ADDB] = "ADDB",
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[CC_OP_ADDW] = "ADDW",
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[CC_OP_ADDL] = "ADDL",
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[CC_OP_ADDQ] = "ADDQ",
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[CC_OP_ADCB] = "ADCB",
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[CC_OP_ADCW] = "ADCW",
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[CC_OP_ADCL] = "ADCL",
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[CC_OP_ADCQ] = "ADCQ",
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[CC_OP_SUBB] = "SUBB",
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[CC_OP_SUBW] = "SUBW",
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[CC_OP_SUBL] = "SUBL",
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[CC_OP_SUBQ] = "SUBQ",
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[CC_OP_SBBB] = "SBBB",
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[CC_OP_SBBW] = "SBBW",
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[CC_OP_SBBL] = "SBBL",
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[CC_OP_SBBQ] = "SBBQ",
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[CC_OP_LOGICB] = "LOGICB",
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[CC_OP_LOGICW] = "LOGICW",
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[CC_OP_LOGICL] = "LOGICL",
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[CC_OP_LOGICQ] = "LOGICQ",
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[CC_OP_INCB] = "INCB",
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[CC_OP_INCW] = "INCW",
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[CC_OP_INCL] = "INCL",
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[CC_OP_INCQ] = "INCQ",
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[CC_OP_DECB] = "DECB",
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[CC_OP_DECW] = "DECW",
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[CC_OP_DECL] = "DECL",
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[CC_OP_DECQ] = "DECQ",
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[CC_OP_SHLB] = "SHLB",
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[CC_OP_SHLW] = "SHLW",
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[CC_OP_SHLL] = "SHLL",
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[CC_OP_SHLQ] = "SHLQ",
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[CC_OP_SARB] = "SARB",
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[CC_OP_SARW] = "SARW",
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[CC_OP_SARL] = "SARL",
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[CC_OP_SARQ] = "SARQ",
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[CC_OP_BMILGB] = "BMILGB",
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[CC_OP_BMILGW] = "BMILGW",
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[CC_OP_BMILGL] = "BMILGL",
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[CC_OP_BMILGQ] = "BMILGQ",
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[CC_OP_POPCNT] = "POPCNT",
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};
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static void
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cpu_x86_dump_seg_cache(CPUX86State *env, FILE *f,
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const char *name, struct SegmentCache *sc)
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{
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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qemu_fprintf(f, "%-3s=%04x %016" PRIx64 " %08x %08x", name,
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sc->selector, sc->base, sc->limit,
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sc->flags & 0x00ffff00);
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} else
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#endif
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{
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qemu_fprintf(f, "%-3s=%04x %08x %08x %08x", name, sc->selector,
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(uint32_t)sc->base, sc->limit,
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sc->flags & 0x00ffff00);
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}
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if (!(env->hflags & HF_PE_MASK) || !(sc->flags & DESC_P_MASK))
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goto done;
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qemu_fprintf(f, " DPL=%d ",
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(sc->flags & DESC_DPL_MASK) >> DESC_DPL_SHIFT);
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if (sc->flags & DESC_S_MASK) {
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if (sc->flags & DESC_CS_MASK) {
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qemu_fprintf(f, (sc->flags & DESC_L_MASK) ? "CS64" :
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((sc->flags & DESC_B_MASK) ? "CS32" : "CS16"));
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qemu_fprintf(f, " [%c%c", (sc->flags & DESC_C_MASK) ? 'C' : '-',
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(sc->flags & DESC_R_MASK) ? 'R' : '-');
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} else {
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qemu_fprintf(f, (sc->flags & DESC_B_MASK
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|| env->hflags & HF_LMA_MASK)
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? "DS " : "DS16");
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qemu_fprintf(f, " [%c%c", (sc->flags & DESC_E_MASK) ? 'E' : '-',
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(sc->flags & DESC_W_MASK) ? 'W' : '-');
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}
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qemu_fprintf(f, "%c]", (sc->flags & DESC_A_MASK) ? 'A' : '-');
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} else {
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static const char *sys_type_name[2][16] = {
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{ /* 32 bit mode */
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"Reserved", "TSS16-avl", "LDT", "TSS16-busy",
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"CallGate16", "TaskGate", "IntGate16", "TrapGate16",
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"Reserved", "TSS32-avl", "Reserved", "TSS32-busy",
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"CallGate32", "Reserved", "IntGate32", "TrapGate32"
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},
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{ /* 64 bit mode */
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"<hiword>", "Reserved", "LDT", "Reserved", "Reserved",
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"Reserved", "Reserved", "Reserved", "Reserved",
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"TSS64-avl", "Reserved", "TSS64-busy", "CallGate64",
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"Reserved", "IntGate64", "TrapGate64"
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}
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};
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qemu_fprintf(f, "%s",
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sys_type_name[(env->hflags & HF_LMA_MASK) ? 1 : 0]
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[(sc->flags & DESC_TYPE_MASK) >> DESC_TYPE_SHIFT]);
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}
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done:
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qemu_fprintf(f, "\n");
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}
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#ifndef CONFIG_USER_ONLY
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/* ARRAY_SIZE check is not required because
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* DeliveryMode(dm) has a size of 3 bit.
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*/
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static inline const char *dm2str(uint32_t dm)
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{
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static const char *str[] = {
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"Fixed",
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"...",
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"SMI",
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"...",
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"NMI",
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"INIT",
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"...",
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"ExtINT"
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};
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return str[dm];
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}
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static void dump_apic_lvt(const char *name, uint32_t lvt, bool is_timer)
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{
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uint32_t dm = (lvt & APIC_LVT_DELIV_MOD) >> APIC_LVT_DELIV_MOD_SHIFT;
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qemu_printf("%s\t 0x%08x %s %-5s %-6s %-7s %-12s %-6s",
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name, lvt,
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lvt & APIC_LVT_INT_POLARITY ? "active-lo" : "active-hi",
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lvt & APIC_LVT_LEVEL_TRIGGER ? "level" : "edge",
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lvt & APIC_LVT_MASKED ? "masked" : "",
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lvt & APIC_LVT_DELIV_STS ? "pending" : "",
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!is_timer ?
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"" : lvt & APIC_LVT_TIMER_PERIODIC ?
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"periodic" : lvt & APIC_LVT_TIMER_TSCDEADLINE ?
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"tsc-deadline" : "one-shot",
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dm2str(dm));
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if (dm != APIC_DM_NMI) {
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qemu_printf(" (vec %u)\n", lvt & APIC_VECTOR_MASK);
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} else {
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qemu_printf("\n");
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}
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}
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/* ARRAY_SIZE check is not required because
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* destination shorthand has a size of 2 bit.
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*/
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static inline const char *shorthand2str(uint32_t shorthand)
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{
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const char *str[] = {
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"no-shorthand", "self", "all-self", "all"
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};
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return str[shorthand];
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}
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static inline uint8_t divider_conf(uint32_t divide_conf)
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{
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uint8_t divide_val = ((divide_conf & 0x8) >> 1) | (divide_conf & 0x3);
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return divide_val == 7 ? 1 : 2 << divide_val;
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}
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static inline void mask2str(char *str, uint32_t val, uint8_t size)
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{
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while (size--) {
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*str++ = (val >> size) & 1 ? '1' : '0';
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}
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*str = 0;
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}
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#define MAX_LOGICAL_APIC_ID_MASK_SIZE 16
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static void dump_apic_icr(APICCommonState *s, CPUX86State *env)
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{
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uint32_t icr = s->icr[0], icr2 = s->icr[1];
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uint8_t dest_shorthand = \
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(icr & APIC_ICR_DEST_SHORT) >> APIC_ICR_DEST_SHORT_SHIFT;
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bool logical_mod = icr & APIC_ICR_DEST_MOD;
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char apic_id_str[MAX_LOGICAL_APIC_ID_MASK_SIZE + 1];
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uint32_t dest_field;
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bool x2apic;
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qemu_printf("ICR\t 0x%08x %s %s %s %s\n",
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icr,
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logical_mod ? "logical" : "physical",
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icr & APIC_ICR_TRIGGER_MOD ? "level" : "edge",
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icr & APIC_ICR_LEVEL ? "assert" : "de-assert",
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shorthand2str(dest_shorthand));
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qemu_printf("ICR2\t 0x%08x", icr2);
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if (dest_shorthand != 0) {
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qemu_printf("\n");
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return;
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}
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x2apic = env->features[FEAT_1_ECX] & CPUID_EXT_X2APIC;
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dest_field = x2apic ? icr2 : icr2 >> APIC_ICR_DEST_SHIFT;
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if (!logical_mod) {
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if (x2apic) {
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qemu_printf(" cpu %u (X2APIC ID)\n", dest_field);
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} else {
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qemu_printf(" cpu %u (APIC ID)\n",
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dest_field & APIC_LOGDEST_XAPIC_ID);
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}
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return;
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}
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if (s->dest_mode == 0xf) { /* flat mode */
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mask2str(apic_id_str, icr2 >> APIC_ICR_DEST_SHIFT, 8);
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qemu_printf(" mask %s (APIC ID)\n", apic_id_str);
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} else if (s->dest_mode == 0) { /* cluster mode */
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if (x2apic) {
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mask2str(apic_id_str, dest_field & APIC_LOGDEST_X2APIC_ID, 16);
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qemu_printf(" cluster %u mask %s (X2APIC ID)\n",
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dest_field >> APIC_LOGDEST_X2APIC_SHIFT, apic_id_str);
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} else {
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mask2str(apic_id_str, dest_field & APIC_LOGDEST_XAPIC_ID, 4);
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qemu_printf(" cluster %u mask %s (APIC ID)\n",
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dest_field >> APIC_LOGDEST_XAPIC_SHIFT, apic_id_str);
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}
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}
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}
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static void dump_apic_interrupt(const char *name, uint32_t *ireg_tab,
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uint32_t *tmr_tab)
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{
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int i, empty = true;
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qemu_printf("%s\t ", name);
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for (i = 0; i < 256; i++) {
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if (apic_get_bit(ireg_tab, i)) {
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qemu_printf("%u%s ", i,
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apic_get_bit(tmr_tab, i) ? "(level)" : "");
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empty = false;
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}
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}
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qemu_printf("%s\n", empty ? "(none)" : "");
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}
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void x86_cpu_dump_local_apic_state(CPUState *cs, int flags)
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{
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X86CPU *cpu = X86_CPU(cs);
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APICCommonState *s = APIC_COMMON(cpu->apic_state);
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if (!s) {
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qemu_printf("local apic state not available\n");
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return;
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}
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uint32_t *lvt = s->lvt;
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qemu_printf("dumping local APIC state for CPU %-2u\n\n",
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CPU(cpu)->cpu_index);
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dump_apic_lvt("LVT0", lvt[APIC_LVT_LINT0], false);
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dump_apic_lvt("LVT1", lvt[APIC_LVT_LINT1], false);
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dump_apic_lvt("LVTPC", lvt[APIC_LVT_PERFORM], false);
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dump_apic_lvt("LVTERR", lvt[APIC_LVT_ERROR], false);
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dump_apic_lvt("LVTTHMR", lvt[APIC_LVT_THERMAL], false);
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dump_apic_lvt("LVTT", lvt[APIC_LVT_TIMER], true);
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qemu_printf("Timer\t DCR=0x%x (divide by %u) initial_count = %u"
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" current_count = %u\n",
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s->divide_conf & APIC_DCR_MASK,
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divider_conf(s->divide_conf),
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s->initial_count, apic_get_current_count(s));
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qemu_printf("SPIV\t 0x%08x APIC %s, focus=%s, spurious vec %u\n",
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s->spurious_vec,
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s->spurious_vec & APIC_SPURIO_ENABLED ? "enabled" : "disabled",
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s->spurious_vec & APIC_SPURIO_FOCUS ? "on" : "off",
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s->spurious_vec & APIC_VECTOR_MASK);
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dump_apic_icr(s, &cpu->env);
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qemu_printf("ESR\t 0x%08x\n", s->esr);
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dump_apic_interrupt("ISR", s->isr, s->tmr);
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dump_apic_interrupt("IRR", s->irr, s->tmr);
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qemu_printf("\nAPR 0x%02x TPR 0x%02x DFR 0x%02x LDR 0x%02x",
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s->arb_id, s->tpr, s->dest_mode, s->log_dest);
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if (s->dest_mode == 0) {
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qemu_printf("(cluster %u: id %u)",
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s->log_dest >> APIC_LOGDEST_XAPIC_SHIFT,
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s->log_dest & APIC_LOGDEST_XAPIC_ID);
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}
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qemu_printf(" PPR 0x%02x\n", apic_get_ppr(s));
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}
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#endif /* !CONFIG_USER_ONLY */
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#define DUMP_CODE_BYTES_TOTAL 50
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#define DUMP_CODE_BYTES_BACKWARD 20
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void x86_cpu_dump_state(CPUState *cs, FILE *f, int flags)
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{
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X86CPU *cpu = X86_CPU(cs);
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CPUX86State *env = &cpu->env;
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int eflags, i, nb;
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static const char *seg_name[6] = { "ES", "CS", "SS", "DS", "FS", "GS" };
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eflags = cpu_compute_eflags(env);
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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qemu_fprintf(f, "RAX=%016" PRIx64 " RBX=%016" PRIx64 " RCX=%016" PRIx64 " RDX=%016" PRIx64 "\n"
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"RSI=%016" PRIx64 " RDI=%016" PRIx64 " RBP=%016" PRIx64 " RSP=%016" PRIx64 "\n"
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"R8 =%016" PRIx64 " R9 =%016" PRIx64 " R10=%016" PRIx64 " R11=%016" PRIx64 "\n"
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"R12=%016" PRIx64 " R13=%016" PRIx64 " R14=%016" PRIx64 " R15=%016" PRIx64 "\n"
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"RIP=%016" PRIx64 " RFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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env->regs[R_EAX],
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env->regs[R_EBX],
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env->regs[R_ECX],
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env->regs[R_EDX],
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env->regs[R_ESI],
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env->regs[R_EDI],
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env->regs[R_EBP],
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env->regs[R_ESP],
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env->regs[8],
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env->regs[9],
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env->regs[10],
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env->regs[11],
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env->regs[12],
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env->regs[13],
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env->regs[14],
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env->regs[15],
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env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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cs->halted);
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} else
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#endif
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{
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qemu_fprintf(f, "EAX=%08x EBX=%08x ECX=%08x EDX=%08x\n"
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"ESI=%08x EDI=%08x EBP=%08x ESP=%08x\n"
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"EIP=%08x EFL=%08x [%c%c%c%c%c%c%c] CPL=%d II=%d A20=%d SMM=%d HLT=%d\n",
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(uint32_t)env->regs[R_EAX],
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(uint32_t)env->regs[R_EBX],
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(uint32_t)env->regs[R_ECX],
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(uint32_t)env->regs[R_EDX],
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(uint32_t)env->regs[R_ESI],
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(uint32_t)env->regs[R_EDI],
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(uint32_t)env->regs[R_EBP],
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(uint32_t)env->regs[R_ESP],
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(uint32_t)env->eip, eflags,
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eflags & DF_MASK ? 'D' : '-',
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eflags & CC_O ? 'O' : '-',
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eflags & CC_S ? 'S' : '-',
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eflags & CC_Z ? 'Z' : '-',
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eflags & CC_A ? 'A' : '-',
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eflags & CC_P ? 'P' : '-',
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eflags & CC_C ? 'C' : '-',
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env->hflags & HF_CPL_MASK,
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(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
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(env->a20_mask >> 20) & 1,
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(env->hflags >> HF_SMM_SHIFT) & 1,
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cs->halted);
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}
|
|
|
|
for(i = 0; i < 6; i++) {
|
|
cpu_x86_dump_seg_cache(env, f, seg_name[i], &env->segs[i]);
|
|
}
|
|
cpu_x86_dump_seg_cache(env, f, "LDT", &env->ldt);
|
|
cpu_x86_dump_seg_cache(env, f, "TR", &env->tr);
|
|
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_LMA_MASK) {
|
|
qemu_fprintf(f, "GDT= %016" PRIx64 " %08x\n",
|
|
env->gdt.base, env->gdt.limit);
|
|
qemu_fprintf(f, "IDT= %016" PRIx64 " %08x\n",
|
|
env->idt.base, env->idt.limit);
|
|
qemu_fprintf(f, "CR0=%08x CR2=%016" PRIx64 " CR3=%016" PRIx64 " CR4=%08x\n",
|
|
(uint32_t)env->cr[0],
|
|
env->cr[2],
|
|
env->cr[3],
|
|
(uint32_t)env->cr[4]);
|
|
for(i = 0; i < 4; i++)
|
|
qemu_fprintf(f, "DR%d=%016" PRIx64 " ", i, env->dr[i]);
|
|
qemu_fprintf(f, "\nDR6=%016" PRIx64 " DR7=%016" PRIx64 "\n",
|
|
env->dr[6], env->dr[7]);
|
|
} else
|
|
#endif
|
|
{
|
|
qemu_fprintf(f, "GDT= %08x %08x\n",
|
|
(uint32_t)env->gdt.base, env->gdt.limit);
|
|
qemu_fprintf(f, "IDT= %08x %08x\n",
|
|
(uint32_t)env->idt.base, env->idt.limit);
|
|
qemu_fprintf(f, "CR0=%08x CR2=%08x CR3=%08x CR4=%08x\n",
|
|
(uint32_t)env->cr[0],
|
|
(uint32_t)env->cr[2],
|
|
(uint32_t)env->cr[3],
|
|
(uint32_t)env->cr[4]);
|
|
for(i = 0; i < 4; i++) {
|
|
qemu_fprintf(f, "DR%d=" TARGET_FMT_lx " ", i, env->dr[i]);
|
|
}
|
|
qemu_fprintf(f, "\nDR6=" TARGET_FMT_lx " DR7=" TARGET_FMT_lx "\n",
|
|
env->dr[6], env->dr[7]);
|
|
}
|
|
if (flags & CPU_DUMP_CCOP) {
|
|
const char *cc_op_name = NULL;
|
|
char cc_op_buf[32];
|
|
|
|
if ((unsigned)env->cc_op < ARRAY_SIZE(cc_op_str)) {
|
|
cc_op_name = cc_op_str[env->cc_op];
|
|
}
|
|
if (cc_op_name == NULL) {
|
|
snprintf(cc_op_buf, sizeof(cc_op_buf), "[%d]", env->cc_op);
|
|
cc_op_name = cc_op_buf;
|
|
}
|
|
#ifdef TARGET_X86_64
|
|
if (env->hflags & HF_CS64_MASK) {
|
|
qemu_fprintf(f, "CCS=%016" PRIx64 " CCD=%016" PRIx64 " CCO=%s\n",
|
|
env->cc_src, env->cc_dst,
|
|
cc_op_name);
|
|
} else
|
|
#endif
|
|
{
|
|
qemu_fprintf(f, "CCS=%08x CCD=%08x CCO=%s\n",
|
|
(uint32_t)env->cc_src, (uint32_t)env->cc_dst,
|
|
cc_op_name);
|
|
}
|
|
}
|
|
qemu_fprintf(f, "EFER=%016" PRIx64 "\n", env->efer);
|
|
if (flags & CPU_DUMP_FPU) {
|
|
int fptag;
|
|
const uint64_t avx512_mask = XSTATE_OPMASK_MASK | \
|
|
XSTATE_ZMM_Hi256_MASK | \
|
|
XSTATE_Hi16_ZMM_MASK | \
|
|
XSTATE_YMM_MASK | XSTATE_SSE_MASK,
|
|
avx_mask = XSTATE_YMM_MASK | XSTATE_SSE_MASK;
|
|
fptag = 0;
|
|
for(i = 0; i < 8; i++) {
|
|
fptag |= ((!env->fptags[i]) << i);
|
|
}
|
|
update_mxcsr_from_sse_status(env);
|
|
qemu_fprintf(f, "FCW=%04x FSW=%04x [ST=%d] FTW=%02x MXCSR=%08x\n",
|
|
env->fpuc,
|
|
(env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11,
|
|
env->fpstt,
|
|
fptag,
|
|
env->mxcsr);
|
|
for(i=0;i<8;i++) {
|
|
CPU_LDoubleU u;
|
|
u.d = env->fpregs[i].d;
|
|
qemu_fprintf(f, "FPR%d=%016" PRIx64 " %04x",
|
|
i, u.l.lower, u.l.upper);
|
|
if ((i & 1) == 1)
|
|
qemu_fprintf(f, "\n");
|
|
else
|
|
qemu_fprintf(f, " ");
|
|
}
|
|
|
|
if ((env->xcr0 & avx512_mask) == avx512_mask) {
|
|
/* XSAVE enabled AVX512 */
|
|
for (i = 0; i < NB_OPMASK_REGS; i++) {
|
|
qemu_fprintf(f, "Opmask%02d=%016"PRIx64"%s", i,
|
|
env->opmask_regs[i], ((i & 3) == 3) ? "\n" : " ");
|
|
}
|
|
|
|
nb = (env->hflags & HF_CS64_MASK) ? 32 : 8;
|
|
for (i = 0; i < nb; i++) {
|
|
qemu_fprintf(f, "ZMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
|
|
" %016"PRIx64" %016"PRIx64" %016"PRIx64
|
|
" %016"PRIx64" %016"PRIx64"\n",
|
|
i,
|
|
env->xmm_regs[i].ZMM_Q(7),
|
|
env->xmm_regs[i].ZMM_Q(6),
|
|
env->xmm_regs[i].ZMM_Q(5),
|
|
env->xmm_regs[i].ZMM_Q(4),
|
|
env->xmm_regs[i].ZMM_Q(3),
|
|
env->xmm_regs[i].ZMM_Q(2),
|
|
env->xmm_regs[i].ZMM_Q(1),
|
|
env->xmm_regs[i].ZMM_Q(0));
|
|
}
|
|
} else if ((env->xcr0 & avx_mask) == avx_mask) {
|
|
/* XSAVE enabled AVX */
|
|
nb = env->hflags & HF_CS64_MASK ? 16 : 8;
|
|
for (i = 0; i < nb; i++) {
|
|
qemu_fprintf(f, "YMM%02d=%016"PRIx64" %016"PRIx64" %016"PRIx64
|
|
" %016"PRIx64"\n", i,
|
|
env->xmm_regs[i].ZMM_Q(3),
|
|
env->xmm_regs[i].ZMM_Q(2),
|
|
env->xmm_regs[i].ZMM_Q(1),
|
|
env->xmm_regs[i].ZMM_Q(0));
|
|
}
|
|
} else { /* SSE and below cases */
|
|
nb = env->hflags & HF_CS64_MASK ? 16 : 8;
|
|
for (i = 0; i < nb; i++) {
|
|
qemu_fprintf(f, "XMM%02d=%016"PRIx64" %016"PRIx64"%s",
|
|
i,
|
|
env->xmm_regs[i].ZMM_Q(1),
|
|
env->xmm_regs[i].ZMM_Q(0),
|
|
(i & 1) ? "\n" : " ");
|
|
}
|
|
}
|
|
}
|
|
if (flags & CPU_DUMP_CODE) {
|
|
target_ulong base = env->segs[R_CS].base + env->eip;
|
|
target_ulong offs = MIN(env->eip, DUMP_CODE_BYTES_BACKWARD);
|
|
uint8_t code;
|
|
char codestr[3];
|
|
|
|
qemu_fprintf(f, "Code=");
|
|
for (i = 0; i < DUMP_CODE_BYTES_TOTAL; i++) {
|
|
if (cpu_memory_rw_debug(cs, base - offs + i, &code, 1, 0) == 0) {
|
|
snprintf(codestr, sizeof(codestr), "%02x", code);
|
|
} else {
|
|
snprintf(codestr, sizeof(codestr), "??");
|
|
}
|
|
qemu_fprintf(f, "%s%s%s%s", i > 0 ? " " : "",
|
|
i == offs ? "<" : "", codestr, i == offs ? ">" : "");
|
|
}
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|