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Peter Maydell b71e2b281a target/arm: Implement ID_AA64PFR2_EL1 ... Currently we define the ID_AA64PFR2_EL1 encoding as reserved (with the required RAZ behaviour for unassigned system registers in the ID register encoding space). Newer architecture versions start to define fields in this ID register, so define the appropriate constants and implement it as an ID register backed by a field in cpu->isar. Since none of our CPUs set that isar field to non-zero, there is no behavioural change here (other than the name exposed to the user via the gdbstub), but this paves the way for implementing the new features that use fields in this register. The fields here are the ones documented in rev L.b of the Arm ARM. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>		2 weeks ago
..
hvf.c	target/arm: Implement ID_AA64PFR2_EL1	2 weeks ago
meson.build	meson: Replace softmmu_ss -> system_ss	2 years ago
sysreg.c.inc	target/arm: Implement ID_AA64PFR2_EL1	2 weeks ago
trace-events	hvf: arm: Remove $pc from trace_hvf_data_abort()	3 months ago
trace.h	target/arm/hvf: Add trace.h header	11 months ago