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868 lines
29 KiB
C
868 lines
29 KiB
C
/*
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* QEMU AArch64 CPU
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*
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* Copyright (c) 2013 Linaro Ltd
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see
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* <http://www.gnu.org/licenses/gpl-2.0.html>
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "cpu.h"
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#include "cpregs.h"
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#include "qemu/module.h"
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#include "qemu/units.h"
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#include "sysemu/kvm.h"
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#include "sysemu/hvf.h"
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#include "sysemu/qtest.h"
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#include "sysemu/tcg.h"
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#include "kvm_arm.h"
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#include "hvf_arm.h"
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#include "qapi/visitor.h"
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#include "hw/qdev-properties.h"
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#include "internals.h"
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#include "cpu-features.h"
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#include "cpregs.h"
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void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
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{
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/*
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* If any vector lengths are explicitly enabled with sve<N> properties,
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* then all other lengths are implicitly disabled. If sve-max-vq is
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* specified then it is the same as explicitly enabling all lengths
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* up to and including the specified maximum, which means all larger
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* lengths will be implicitly disabled. If no sve<N> properties
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* are enabled and sve-max-vq is not specified, then all lengths not
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* explicitly disabled will be enabled. Additionally, all power-of-two
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* vector lengths less than the maximum enabled length will be
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* automatically enabled and all vector lengths larger than the largest
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* disabled power-of-two vector length will be automatically disabled.
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* Errors are generated if the user provided input that interferes with
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* any of the above. Finally, if SVE is not disabled, then at least one
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* vector length must be enabled.
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*/
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uint32_t vq_map = cpu->sve_vq.map;
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uint32_t vq_init = cpu->sve_vq.init;
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uint32_t vq_supported;
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uint32_t vq_mask = 0;
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uint32_t tmp, vq, max_vq = 0;
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/*
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* CPU models specify a set of supported vector lengths which are
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* enabled by default. Attempting to enable any vector length not set
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* in the supported bitmap results in an error. When KVM is enabled we
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* fetch the supported bitmap from the host.
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*/
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if (kvm_enabled()) {
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if (kvm_arm_sve_supported()) {
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cpu->sve_vq.supported = kvm_arm_sve_get_vls(cpu);
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vq_supported = cpu->sve_vq.supported;
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} else {
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assert(!cpu_isar_feature(aa64_sve, cpu));
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vq_supported = 0;
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}
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} else {
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vq_supported = cpu->sve_vq.supported;
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}
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/*
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* Process explicit sve<N> properties.
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* From the properties, sve_vq_map<N> implies sve_vq_init<N>.
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* Check first for any sve<N> enabled.
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*/
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if (vq_map != 0) {
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max_vq = 32 - clz32(vq_map);
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vq_mask = MAKE_64BIT_MASK(0, max_vq);
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if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) {
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error_setg(errp, "cannot enable sve%d", max_vq * 128);
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error_append_hint(errp, "sve%d is larger than the maximum vector "
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"length, sve-max-vq=%d (%d bits)\n",
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max_vq * 128, cpu->sve_max_vq,
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cpu->sve_max_vq * 128);
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return;
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}
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if (kvm_enabled()) {
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/*
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* For KVM we have to automatically enable all supported uninitialized
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* lengths, even when the smaller lengths are not all powers-of-two.
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*/
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vq_map |= vq_supported & ~vq_init & vq_mask;
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} else {
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/* Propagate enabled bits down through required powers-of-two. */
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vq_map |= SVE_VQ_POW2_MAP & ~vq_init & vq_mask;
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}
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} else if (cpu->sve_max_vq == 0) {
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/*
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* No explicit bits enabled, and no implicit bits from sve-max-vq.
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*/
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if (!cpu_isar_feature(aa64_sve, cpu)) {
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/*
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* SVE is disabled and so are all vector lengths. Good.
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* Disable all SVE extensions as well.
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*/
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cpu->isar.id_aa64zfr0 = 0;
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return;
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}
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if (kvm_enabled()) {
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/* Disabling a supported length disables all larger lengths. */
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tmp = vq_init & vq_supported;
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} else {
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/* Disabling a power-of-two disables all larger lengths. */
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tmp = vq_init & SVE_VQ_POW2_MAP;
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}
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vq = ctz32(tmp) + 1;
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max_vq = vq <= ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ;
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vq_mask = max_vq > 0 ? MAKE_64BIT_MASK(0, max_vq) : 0;
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vq_map = vq_supported & ~vq_init & vq_mask;
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if (vq_map == 0) {
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error_setg(errp, "cannot disable sve%d", vq * 128);
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error_append_hint(errp, "Disabling sve%d results in all "
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"vector lengths being disabled.\n",
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vq * 128);
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error_append_hint(errp, "With SVE enabled, at least one "
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"vector length must be enabled.\n");
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return;
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}
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max_vq = 32 - clz32(vq_map);
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vq_mask = MAKE_64BIT_MASK(0, max_vq);
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}
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/*
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* Process the sve-max-vq property.
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* Note that we know from the above that no bit above
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* sve-max-vq is currently set.
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*/
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if (cpu->sve_max_vq != 0) {
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max_vq = cpu->sve_max_vq;
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vq_mask = MAKE_64BIT_MASK(0, max_vq);
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if (vq_init & ~vq_map & (1 << (max_vq - 1))) {
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error_setg(errp, "cannot disable sve%d", max_vq * 128);
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error_append_hint(errp, "The maximum vector length must be "
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"enabled, sve-max-vq=%d (%d bits)\n",
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max_vq, max_vq * 128);
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return;
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}
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/* Set all bits not explicitly set within sve-max-vq. */
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vq_map |= ~vq_init & vq_mask;
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}
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/*
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* We should know what max-vq is now. Also, as we're done
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* manipulating sve-vq-map, we ensure any bits above max-vq
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* are clear, just in case anybody looks.
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*/
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assert(max_vq != 0);
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assert(vq_mask != 0);
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vq_map &= vq_mask;
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/* Ensure the set of lengths matches what is supported. */
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tmp = vq_map ^ (vq_supported & vq_mask);
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if (tmp) {
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vq = 32 - clz32(tmp);
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if (vq_map & (1 << (vq - 1))) {
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if (cpu->sve_max_vq) {
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error_setg(errp, "cannot set sve-max-vq=%d", cpu->sve_max_vq);
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error_append_hint(errp, "This CPU does not support "
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"the vector length %d-bits.\n", vq * 128);
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error_append_hint(errp, "It may not be possible to use "
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"sve-max-vq with this CPU. Try "
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"using only sve<N> properties.\n");
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} else {
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error_setg(errp, "cannot enable sve%d", vq * 128);
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if (vq_supported) {
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error_append_hint(errp, "This CPU does not support "
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"the vector length %d-bits.\n", vq * 128);
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} else {
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error_append_hint(errp, "SVE not supported by KVM "
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"on this host\n");
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}
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}
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return;
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} else {
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if (kvm_enabled()) {
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error_setg(errp, "cannot disable sve%d", vq * 128);
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error_append_hint(errp, "The KVM host requires all "
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"supported vector lengths smaller "
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"than %d bits to also be enabled.\n",
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max_vq * 128);
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return;
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} else {
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/* Ensure all required powers-of-two are enabled. */
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tmp = SVE_VQ_POW2_MAP & vq_mask & ~vq_map;
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if (tmp) {
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vq = 32 - clz32(tmp);
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error_setg(errp, "cannot disable sve%d", vq * 128);
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error_append_hint(errp, "sve%d is required as it "
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"is a power-of-two length smaller "
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"than the maximum, sve%d\n",
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vq * 128, max_vq * 128);
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return;
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}
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}
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}
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}
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/*
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* Now that we validated all our vector lengths, the only question
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* left to answer is if we even want SVE at all.
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*/
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if (!cpu_isar_feature(aa64_sve, cpu)) {
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error_setg(errp, "cannot enable sve%d", max_vq * 128);
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error_append_hint(errp, "SVE must be enabled to enable vector "
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"lengths.\n");
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error_append_hint(errp, "Add sve=on to the CPU property list.\n");
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return;
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}
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/* From now on sve_max_vq is the actual maximum supported length. */
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cpu->sve_max_vq = max_vq;
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cpu->sve_vq.map = vq_map;
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}
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/*
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* Note that cpu_arm_{get,set}_vq cannot use the simpler
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* object_property_add_bool interface because they make use of the
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* contents of "name" to determine which bit on which to operate.
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*/
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static void cpu_arm_get_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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ARMVQMap *vq_map = opaque;
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uint32_t vq = atoi(&name[3]) / 128;
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bool sve = vq_map == &cpu->sve_vq;
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bool value;
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/* All vector lengths are disabled when feature is off. */
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if (sve
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? !cpu_isar_feature(aa64_sve, cpu)
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: !cpu_isar_feature(aa64_sme, cpu)) {
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value = false;
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} else {
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value = extract32(vq_map->map, vq - 1, 1);
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}
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visit_type_bool(v, name, &value, errp);
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}
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static void cpu_arm_set_vq(Object *obj, Visitor *v, const char *name,
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void *opaque, Error **errp)
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{
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ARMVQMap *vq_map = opaque;
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uint32_t vq = atoi(&name[3]) / 128;
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bool value;
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if (!visit_type_bool(v, name, &value, errp)) {
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return;
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}
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vq_map->map = deposit32(vq_map->map, vq - 1, 1, value);
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vq_map->init |= 1 << (vq - 1);
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}
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static bool cpu_arm_get_sve(Object *obj, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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return cpu_isar_feature(aa64_sve, cpu);
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}
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static void cpu_arm_set_sve(Object *obj, bool value, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint64_t t;
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if (value && kvm_enabled() && !kvm_arm_sve_supported()) {
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error_setg(errp, "'sve' feature not supported by KVM on this host");
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return;
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}
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t = cpu->isar.id_aa64pfr0;
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t = FIELD_DP64(t, ID_AA64PFR0, SVE, value);
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cpu->isar.id_aa64pfr0 = t;
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}
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void arm_cpu_sme_finalize(ARMCPU *cpu, Error **errp)
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{
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uint32_t vq_map = cpu->sme_vq.map;
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uint32_t vq_init = cpu->sme_vq.init;
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uint32_t vq_supported = cpu->sme_vq.supported;
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uint32_t vq;
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if (vq_map == 0) {
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if (!cpu_isar_feature(aa64_sme, cpu)) {
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cpu->isar.id_aa64smfr0 = 0;
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return;
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}
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/* TODO: KVM will require limitations via SMCR_EL2. */
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vq_map = vq_supported & ~vq_init;
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if (vq_map == 0) {
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vq = ctz32(vq_supported) + 1;
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error_setg(errp, "cannot disable sme%d", vq * 128);
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error_append_hint(errp, "All SME vector lengths are disabled.\n");
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error_append_hint(errp, "With SME enabled, at least one "
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"vector length must be enabled.\n");
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return;
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}
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} else {
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if (!cpu_isar_feature(aa64_sme, cpu)) {
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vq = 32 - clz32(vq_map);
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error_setg(errp, "cannot enable sme%d", vq * 128);
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error_append_hint(errp, "SME must be enabled to enable "
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"vector lengths.\n");
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error_append_hint(errp, "Add sme=on to the CPU property list.\n");
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return;
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}
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/* TODO: KVM will require limitations via SMCR_EL2. */
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}
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cpu->sme_vq.map = vq_map;
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}
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static bool cpu_arm_get_sme(Object *obj, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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return cpu_isar_feature(aa64_sme, cpu);
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}
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static void cpu_arm_set_sme(Object *obj, bool value, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint64_t t;
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t = cpu->isar.id_aa64pfr1;
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t = FIELD_DP64(t, ID_AA64PFR1, SME, value);
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cpu->isar.id_aa64pfr1 = t;
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}
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static bool cpu_arm_get_sme_fa64(Object *obj, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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return cpu_isar_feature(aa64_sme, cpu) &&
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cpu_isar_feature(aa64_sme_fa64, cpu);
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}
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static void cpu_arm_set_sme_fa64(Object *obj, bool value, Error **errp)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint64_t t;
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t = cpu->isar.id_aa64smfr0;
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t = FIELD_DP64(t, ID_AA64SMFR0, FA64, value);
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cpu->isar.id_aa64smfr0 = t;
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}
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#ifdef CONFIG_USER_ONLY
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/* Mirror linux /proc/sys/abi/{sve,sme}_default_vector_length. */
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static void cpu_arm_set_default_vec_len(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
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{
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uint32_t *ptr_default_vq = opaque;
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int32_t default_len, default_vq, remainder;
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if (!visit_type_int32(v, name, &default_len, errp)) {
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return;
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}
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|
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/* Undocumented, but the kernel allows -1 to indicate "maximum". */
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if (default_len == -1) {
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*ptr_default_vq = ARM_MAX_VQ;
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return;
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}
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default_vq = default_len / 16;
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remainder = default_len % 16;
|
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|
|
/*
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* Note that the 512 max comes from include/uapi/asm/sve_context.h
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* and is the maximum architectural width of ZCR_ELx.LEN.
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*/
|
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if (remainder || default_vq < 1 || default_vq > 512) {
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ARMCPU *cpu = ARM_CPU(obj);
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const char *which =
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(ptr_default_vq == &cpu->sve_default_vq ? "sve" : "sme");
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error_setg(errp, "cannot set %s-default-vector-length", which);
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if (remainder) {
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error_append_hint(errp, "Vector length not a multiple of 16\n");
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} else if (default_vq < 1) {
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error_append_hint(errp, "Vector length smaller than 16\n");
|
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} else {
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error_append_hint(errp, "Vector length larger than %d\n",
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512 * 16);
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}
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return;
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}
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*ptr_default_vq = default_vq;
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}
|
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|
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static void cpu_arm_get_default_vec_len(Object *obj, Visitor *v,
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const char *name, void *opaque,
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Error **errp)
|
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{
|
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uint32_t *ptr_default_vq = opaque;
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int32_t value = *ptr_default_vq * 16;
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visit_type_int32(v, name, &value, errp);
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}
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#endif
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void aarch64_add_sve_properties(Object *obj)
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{
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ARMCPU *cpu = ARM_CPU(obj);
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uint32_t vq;
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object_property_add_bool(obj, "sve", cpu_arm_get_sve, cpu_arm_set_sve);
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for (vq = 1; vq <= ARM_MAX_VQ; ++vq) {
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char name[8];
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snprintf(name, sizeof(name), "sve%d", vq * 128);
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object_property_add(obj, name, "bool", cpu_arm_get_vq,
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cpu_arm_set_vq, NULL, &cpu->sve_vq);
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}
|
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|
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#ifdef CONFIG_USER_ONLY
|
|
/* Mirror linux /proc/sys/abi/sve_default_vector_length. */
|
|
object_property_add(obj, "sve-default-vector-length", "int32",
|
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cpu_arm_get_default_vec_len,
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cpu_arm_set_default_vec_len, NULL,
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&cpu->sve_default_vq);
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|
#endif
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}
|
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|
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void aarch64_add_sme_properties(Object *obj)
|
|
{
|
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ARMCPU *cpu = ARM_CPU(obj);
|
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uint32_t vq;
|
|
|
|
object_property_add_bool(obj, "sme", cpu_arm_get_sme, cpu_arm_set_sme);
|
|
object_property_add_bool(obj, "sme_fa64", cpu_arm_get_sme_fa64,
|
|
cpu_arm_set_sme_fa64);
|
|
|
|
for (vq = 1; vq <= ARM_MAX_VQ; vq <<= 1) {
|
|
char name[8];
|
|
snprintf(name, sizeof(name), "sme%d", vq * 128);
|
|
object_property_add(obj, name, "bool", cpu_arm_get_vq,
|
|
cpu_arm_set_vq, NULL, &cpu->sme_vq);
|
|
}
|
|
|
|
#ifdef CONFIG_USER_ONLY
|
|
/* Mirror linux /proc/sys/abi/sme_default_vector_length. */
|
|
object_property_add(obj, "sme-default-vector-length", "int32",
|
|
cpu_arm_get_default_vec_len,
|
|
cpu_arm_set_default_vec_len, NULL,
|
|
&cpu->sme_default_vq);
|
|
#endif
|
|
}
|
|
|
|
void arm_cpu_pauth_finalize(ARMCPU *cpu, Error **errp)
|
|
{
|
|
ARMPauthFeature features = cpu_isar_feature(pauth_feature, cpu);
|
|
uint64_t isar1, isar2;
|
|
|
|
/*
|
|
* These properties enable or disable Pauth as a whole, or change
|
|
* the pauth algorithm, but do not change the set of features that
|
|
* are present. We have saved a copy of those features above and
|
|
* will now place it into the field that chooses the algorithm.
|
|
*
|
|
* Begin by disabling all fields.
|
|
*/
|
|
isar1 = cpu->isar.id_aa64isar1;
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, 0);
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 0);
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, 0);
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 0);
|
|
|
|
isar2 = cpu->isar.id_aa64isar2;
|
|
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, 0);
|
|
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 0);
|
|
|
|
if (kvm_enabled() || hvf_enabled()) {
|
|
/*
|
|
* Exit early if PAuth is enabled and fall through to disable it.
|
|
* The algorithm selection properties are not present.
|
|
*/
|
|
if (cpu->prop_pauth) {
|
|
if (features == 0) {
|
|
error_setg(errp, "'pauth' feature not supported by "
|
|
"%s on this host", current_accel_name());
|
|
}
|
|
return;
|
|
}
|
|
} else {
|
|
/* Pauth properties are only present when the model supports it. */
|
|
if (features == 0) {
|
|
assert(!cpu->prop_pauth);
|
|
return;
|
|
}
|
|
|
|
if (cpu->prop_pauth) {
|
|
if (cpu->prop_pauth_impdef && cpu->prop_pauth_qarma3) {
|
|
error_setg(errp,
|
|
"cannot enable both pauth-impdef and pauth-qarma3");
|
|
return;
|
|
}
|
|
|
|
if (cpu->prop_pauth_impdef) {
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, API, features);
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPI, 1);
|
|
} else if (cpu->prop_pauth_qarma3) {
|
|
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, APA3, features);
|
|
isar2 = FIELD_DP64(isar2, ID_AA64ISAR2, GPA3, 1);
|
|
} else {
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, APA, features);
|
|
isar1 = FIELD_DP64(isar1, ID_AA64ISAR1, GPA, 1);
|
|
}
|
|
} else if (cpu->prop_pauth_impdef || cpu->prop_pauth_qarma3) {
|
|
error_setg(errp, "cannot enable pauth-impdef or "
|
|
"pauth-qarma3 without pauth");
|
|
error_append_hint(errp, "Add pauth=on to the CPU property list.\n");
|
|
}
|
|
}
|
|
|
|
cpu->isar.id_aa64isar1 = isar1;
|
|
cpu->isar.id_aa64isar2 = isar2;
|
|
}
|
|
|
|
static Property arm_cpu_pauth_property =
|
|
DEFINE_PROP_BOOL("pauth", ARMCPU, prop_pauth, true);
|
|
static Property arm_cpu_pauth_impdef_property =
|
|
DEFINE_PROP_BOOL("pauth-impdef", ARMCPU, prop_pauth_impdef, false);
|
|
static Property arm_cpu_pauth_qarma3_property =
|
|
DEFINE_PROP_BOOL("pauth-qarma3", ARMCPU, prop_pauth_qarma3, false);
|
|
|
|
void aarch64_add_pauth_properties(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
/* Default to PAUTH on, with the architected algorithm on TCG. */
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_property);
|
|
if (kvm_enabled() || hvf_enabled()) {
|
|
/*
|
|
* Mirror PAuth support from the probed sysregs back into the
|
|
* property for KVM or hvf. Is it just a bit backward? Yes it is!
|
|
* Note that prop_pauth is true whether the host CPU supports the
|
|
* architected QARMA5 algorithm or the IMPDEF one. We don't
|
|
* provide the separate pauth-impdef property for KVM or hvf,
|
|
* only for TCG.
|
|
*/
|
|
cpu->prop_pauth = cpu_isar_feature(aa64_pauth, cpu);
|
|
} else {
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_impdef_property);
|
|
qdev_property_add_static(DEVICE(obj), &arm_cpu_pauth_qarma3_property);
|
|
}
|
|
}
|
|
|
|
void arm_cpu_lpa2_finalize(ARMCPU *cpu, Error **errp)
|
|
{
|
|
uint64_t t;
|
|
|
|
/*
|
|
* We only install the property for tcg -cpu max; this is the
|
|
* only situation in which the cpu field can be true.
|
|
*/
|
|
if (!cpu->prop_lpa2) {
|
|
return;
|
|
}
|
|
|
|
t = cpu->isar.id_aa64mmfr0;
|
|
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16, 2); /* 16k pages w/ LPA2 */
|
|
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4, 1); /* 4k pages w/ LPA2 */
|
|
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN16_2, 3); /* 16k stage2 w/ LPA2 */
|
|
t = FIELD_DP64(t, ID_AA64MMFR0, TGRAN4_2, 3); /* 4k stage2 w/ LPA2 */
|
|
cpu->isar.id_aa64mmfr0 = t;
|
|
}
|
|
|
|
static void aarch64_a57_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,cortex-a57";
|
|
set_feature(&cpu->env, ARM_FEATURE_V8);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
|
set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
|
|
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
|
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A57;
|
|
cpu->midr = 0x411fd070;
|
|
cpu->revidr = 0x00000000;
|
|
cpu->reset_fpsid = 0x41034070;
|
|
cpu->isar.mvfr0 = 0x10110222;
|
|
cpu->isar.mvfr1 = 0x12111111;
|
|
cpu->isar.mvfr2 = 0x00000043;
|
|
cpu->ctr = 0x8444c004;
|
|
cpu->reset_sctlr = 0x00c50838;
|
|
cpu->isar.id_pfr0 = 0x00000131;
|
|
cpu->isar.id_pfr1 = 0x00011011;
|
|
cpu->isar.id_dfr0 = 0x03010066;
|
|
cpu->id_afr0 = 0x00000000;
|
|
cpu->isar.id_mmfr0 = 0x10101105;
|
|
cpu->isar.id_mmfr1 = 0x40000000;
|
|
cpu->isar.id_mmfr2 = 0x01260000;
|
|
cpu->isar.id_mmfr3 = 0x02102211;
|
|
cpu->isar.id_isar0 = 0x02101110;
|
|
cpu->isar.id_isar1 = 0x13112111;
|
|
cpu->isar.id_isar2 = 0x21232042;
|
|
cpu->isar.id_isar3 = 0x01112131;
|
|
cpu->isar.id_isar4 = 0x00011142;
|
|
cpu->isar.id_isar5 = 0x00011121;
|
|
cpu->isar.id_isar6 = 0;
|
|
cpu->isar.id_aa64pfr0 = 0x00002222;
|
|
cpu->isar.id_aa64dfr0 = 0x10305106;
|
|
cpu->isar.id_aa64isar0 = 0x00011120;
|
|
cpu->isar.id_aa64mmfr0 = 0x00001124;
|
|
cpu->isar.dbgdidr = 0x3516d000;
|
|
cpu->isar.dbgdevid = 0x01110f13;
|
|
cpu->isar.dbgdevid1 = 0x2;
|
|
cpu->isar.reset_pmcr_el0 = 0x41013000;
|
|
cpu->clidr = 0x0a200023;
|
|
/* 32KB L1 dcache */
|
|
cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
|
|
/* 48KB L1 icache */
|
|
cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 3, 64, 48 * KiB, 2);
|
|
/* 2048KB L2 cache */
|
|
cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 2 * MiB, 7);
|
|
cpu->dcz_blocksize = 4; /* 64 bytes */
|
|
cpu->gic_num_lrs = 4;
|
|
cpu->gic_vpribits = 5;
|
|
cpu->gic_vprebits = 5;
|
|
cpu->gic_pribits = 5;
|
|
define_cortex_a72_a57_a53_cp_reginfo(cpu);
|
|
}
|
|
|
|
static void aarch64_a53_initfn(Object *obj)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
cpu->dtb_compatible = "arm,cortex-a53";
|
|
set_feature(&cpu->env, ARM_FEATURE_V8);
|
|
set_feature(&cpu->env, ARM_FEATURE_NEON);
|
|
set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
|
|
set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ);
|
|
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL2);
|
|
set_feature(&cpu->env, ARM_FEATURE_EL3);
|
|
set_feature(&cpu->env, ARM_FEATURE_PMU);
|
|
cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A53;
|
|
cpu->midr = 0x410fd034;
|
|
cpu->revidr = 0x00000100;
|
|
cpu->reset_fpsid = 0x41034070;
|
|
cpu->isar.mvfr0 = 0x10110222;
|
|
cpu->isar.mvfr1 = 0x12111111;
|
|
cpu->isar.mvfr2 = 0x00000043;
|
|
cpu->ctr = 0x84448004; /* L1Ip = VIPT */
|
|
cpu->reset_sctlr = 0x00c50838;
|
|
cpu->isar.id_pfr0 = 0x00000131;
|
|
cpu->isar.id_pfr1 = 0x00011011;
|
|
cpu->isar.id_dfr0 = 0x03010066;
|
|
cpu->id_afr0 = 0x00000000;
|
|
cpu->isar.id_mmfr0 = 0x10101105;
|
|
cpu->isar.id_mmfr1 = 0x40000000;
|
|
cpu->isar.id_mmfr2 = 0x01260000;
|
|
cpu->isar.id_mmfr3 = 0x02102211;
|
|
cpu->isar.id_isar0 = 0x02101110;
|
|
cpu->isar.id_isar1 = 0x13112111;
|
|
cpu->isar.id_isar2 = 0x21232042;
|
|
cpu->isar.id_isar3 = 0x01112131;
|
|
cpu->isar.id_isar4 = 0x00011142;
|
|
cpu->isar.id_isar5 = 0x00011121;
|
|
cpu->isar.id_isar6 = 0;
|
|
cpu->isar.id_aa64pfr0 = 0x00002222;
|
|
cpu->isar.id_aa64dfr0 = 0x10305106;
|
|
cpu->isar.id_aa64isar0 = 0x00011120;
|
|
cpu->isar.id_aa64mmfr0 = 0x00001122; /* 40 bit physical addr */
|
|
cpu->isar.dbgdidr = 0x3516d000;
|
|
cpu->isar.dbgdevid = 0x00110f13;
|
|
cpu->isar.dbgdevid1 = 0x1;
|
|
cpu->isar.reset_pmcr_el0 = 0x41033000;
|
|
cpu->clidr = 0x0a200023;
|
|
/* 32KB L1 dcache */
|
|
cpu->ccsidr[0] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 32 * KiB, 7);
|
|
/* 32KB L1 icache */
|
|
cpu->ccsidr[1] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 1, 64, 32 * KiB, 2);
|
|
/* 1024KB L2 cache */
|
|
cpu->ccsidr[2] = make_ccsidr(CCSIDR_FORMAT_LEGACY, 16, 64, 1 * MiB, 7);
|
|
cpu->dcz_blocksize = 4; /* 64 bytes */
|
|
cpu->gic_num_lrs = 4;
|
|
cpu->gic_vpribits = 5;
|
|
cpu->gic_vprebits = 5;
|
|
cpu->gic_pribits = 5;
|
|
define_cortex_a72_a57_a53_cp_reginfo(cpu);
|
|
}
|
|
|
|
static void aarch64_host_initfn(Object *obj)
|
|
{
|
|
#if defined(CONFIG_KVM)
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
kvm_arm_set_cpu_features_from_host(cpu);
|
|
if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
|
|
aarch64_add_sve_properties(obj);
|
|
aarch64_add_pauth_properties(obj);
|
|
}
|
|
#elif defined(CONFIG_HVF)
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
hvf_arm_set_cpu_features_from_host(cpu);
|
|
aarch64_add_pauth_properties(obj);
|
|
#else
|
|
g_assert_not_reached();
|
|
#endif
|
|
}
|
|
|
|
static void aarch64_max_initfn(Object *obj)
|
|
{
|
|
if (kvm_enabled() || hvf_enabled()) {
|
|
/* With KVM or HVF, '-cpu max' is identical to '-cpu host' */
|
|
aarch64_host_initfn(obj);
|
|
return;
|
|
}
|
|
|
|
if (tcg_enabled() || qtest_enabled()) {
|
|
aarch64_a57_initfn(obj);
|
|
}
|
|
|
|
/* '-cpu max' for TCG: we currently do this as "A57 with extra things" */
|
|
if (tcg_enabled()) {
|
|
aarch64_max_tcg_initfn(obj);
|
|
}
|
|
}
|
|
|
|
static const ARMCPUInfo aarch64_cpus[] = {
|
|
{ .name = "cortex-a57", .initfn = aarch64_a57_initfn },
|
|
{ .name = "cortex-a53", .initfn = aarch64_a53_initfn },
|
|
{ .name = "max", .initfn = aarch64_max_initfn },
|
|
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
|
|
{ .name = "host", .initfn = aarch64_host_initfn },
|
|
#endif
|
|
};
|
|
|
|
static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
return arm_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
}
|
|
|
|
static void aarch64_cpu_set_aarch64(Object *obj, bool value, Error **errp)
|
|
{
|
|
ARMCPU *cpu = ARM_CPU(obj);
|
|
|
|
/* At this time, this property is only allowed if KVM is enabled. This
|
|
* restriction allows us to avoid fixing up functionality that assumes a
|
|
* uniform execution state like do_interrupt.
|
|
*/
|
|
if (value == false) {
|
|
if (!kvm_enabled() || !kvm_arm_aarch32_supported()) {
|
|
error_setg(errp, "'aarch64' feature cannot be disabled "
|
|
"unless KVM is enabled and 32-bit EL1 "
|
|
"is supported");
|
|
return;
|
|
}
|
|
unset_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
} else {
|
|
set_feature(&cpu->env, ARM_FEATURE_AARCH64);
|
|
}
|
|
}
|
|
|
|
static void aarch64_cpu_finalizefn(Object *obj)
|
|
{
|
|
}
|
|
|
|
static const gchar *aarch64_gdb_arch_name(CPUState *cs)
|
|
{
|
|
return "aarch64";
|
|
}
|
|
|
|
static void aarch64_cpu_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
CPUClass *cc = CPU_CLASS(oc);
|
|
|
|
cc->gdb_read_register = aarch64_cpu_gdb_read_register;
|
|
cc->gdb_write_register = aarch64_cpu_gdb_write_register;
|
|
cc->gdb_core_xml_file = "aarch64-core.xml";
|
|
cc->gdb_arch_name = aarch64_gdb_arch_name;
|
|
|
|
object_class_property_add_bool(oc, "aarch64", aarch64_cpu_get_aarch64,
|
|
aarch64_cpu_set_aarch64);
|
|
object_class_property_set_description(oc, "aarch64",
|
|
"Set on/off to enable/disable aarch64 "
|
|
"execution state ");
|
|
}
|
|
|
|
static void aarch64_cpu_instance_init(Object *obj)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_GET_CLASS(obj);
|
|
|
|
acc->info->initfn(obj);
|
|
arm_cpu_post_init(obj);
|
|
}
|
|
|
|
static void cpu_register_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
ARMCPUClass *acc = ARM_CPU_CLASS(oc);
|
|
|
|
acc->info = data;
|
|
}
|
|
|
|
void aarch64_cpu_register(const ARMCPUInfo *info)
|
|
{
|
|
TypeInfo type_info = {
|
|
.parent = TYPE_AARCH64_CPU,
|
|
.instance_init = aarch64_cpu_instance_init,
|
|
.class_init = info->class_init ?: cpu_register_class_init,
|
|
.class_data = (void *)info,
|
|
};
|
|
|
|
type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
|
|
type_register(&type_info);
|
|
g_free((void *)type_info.name);
|
|
}
|
|
|
|
static const TypeInfo aarch64_cpu_type_info = {
|
|
.name = TYPE_AARCH64_CPU,
|
|
.parent = TYPE_ARM_CPU,
|
|
.instance_finalize = aarch64_cpu_finalizefn,
|
|
.abstract = true,
|
|
.class_init = aarch64_cpu_class_init,
|
|
};
|
|
|
|
static void aarch64_cpu_register_types(void)
|
|
{
|
|
size_t i;
|
|
|
|
type_register_static(&aarch64_cpu_type_info);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(aarch64_cpus); ++i) {
|
|
aarch64_cpu_register(&aarch64_cpus[i]);
|
|
}
|
|
}
|
|
|
|
type_init(aarch64_cpu_register_types)
|