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67 lines
1.4 KiB
C
67 lines
1.4 KiB
C
/*
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* Coherent Processing System emulation.
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* Copyright (c) 2025 MIPS
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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*/
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#ifndef RISCV_CPS_H
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#define RISCV_CPS_H
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#include "hw/core/sysbus.h"
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#include "hw/misc/riscv_cmgcr.h"
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#include "hw/misc/riscv_cpc.h"
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#include "target/riscv/cpu.h"
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#include "qom/object.h"
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#define TYPE_RISCV_CPS "riscv-cps"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPSState, RISCV_CPS)
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/* The model supports up to 64 harts. */
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#define MAX_HARTS 64
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/* The global CM base for the boston-aia model. */
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#define GLOBAL_CM_BASE 0x16100000
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/* The CM block is 512 KiB. */
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#define CM_SIZE (1 << 19)
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/*
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* The mhartid bits has cluster at bit 16, core at bit 4, and hart at
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* bit 0.
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*/
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#define MHARTID_CLUSTER_SHIFT 16
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#define MHARTID_CORE_SHIFT 4
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#define MHARTID_HART_SHIFT 0
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#define APLIC_NUM_SOURCES 0x35 /* Arbitray maximum number of interrupts. */
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#define APLIC_NUM_PRIO_BITS 3
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#define AIA_PLIC_M_OFFSET 0x40000
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#define AIA_PLIC_M_SIZE 0x8000
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#define AIA_PLIC_S_OFFSET 0x60000
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#define AIA_PLIC_S_SIZE 0x8000
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#define AIA_CLINT_OFFSET 0x50000
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typedef struct RISCVCPSState {
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SysBusDevice parent_obj;
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uint32_t num_vp;
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uint32_t num_hart;
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uint32_t num_core;
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uint64_t gcr_base;
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char *cpu_type;
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MemoryRegion container;
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RISCVGCRState gcr;
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RISCVCPCState cpc;
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DeviceState *aplic;
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CPUState **cpus;
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} RISCVCPSState;
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#endif
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