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Zhenzhong Duan 860bb8b925 hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class ... RISCVIOMMUPciClass and RISCVIOMMUSysClass are defined with missed parent class, class_init on them may corrupt their parent class fields. It's lucky that parent_realize and parent_phases are not initialized or used until now, so just remove the definitions. They can be added back when really necessary. Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20250606092406.229833-6-zhenzhong.duan@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		3 weeks ago
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boot.h	hw/riscv: Add the checking if DTB overlaps to kernel or initrd	6 months ago
boot_opensbi.h	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	8 months ago
iommu.h	hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class	3 weeks ago
microchip_pfsoc.h	hw/riscv: Configurable MPFS CLINT timebase freq	1 month ago
numa.h	include: Rename sysemu/ -> system/	6 months ago
opentitan.h	hw/riscv/opentitan: Correct OpenTitanState parent type/size	2 years ago
riscv_hart.h	target/riscv: Handle Smrnmi interrupt and exception	5 months ago
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	3 years ago
sifive_cpu.h	riscv: Add a sifive_cpu.h to include both E and U cpu type defines	6 years ago
sifive_e.h	hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.	2 years ago
sifive_u.h	hw/riscv: Move the dtb load bits outside of create_fdt()	2 years ago
spike.h	hw/riscv/spike: use 'fdt' from MachineState	2 years ago
virt.h	hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure	1 month ago