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Huang Borong 29abd3d112 hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype ... This implementation provides emulation for the Xiangshan Kunminghu FPGA prototype platform, including support for UART, CLINT, IMSIC, and APLIC devices. More details can be found at https://github.com/OpenXiangShan/XiangShan Signed-off-by: qinshaoqing <qinshaoqing@bosc.ac.cn> Signed-off-by: Yang Wang <wangyang@bosc.ac.cn> Signed-off-by: Yu Hu <819258943@qq.com> Signed-off-by: Ran Wang <wangran@bosc.ac.cn> Signed-off-by: Borong Huang <3543977024@qq.com> Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Message-ID: <20250617074222.17618-1-wangran@bosc.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2 weeks ago
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boot.h	hw/riscv: Add the checking if DTB overlaps to kernel or initrd	7 months ago
boot_opensbi.h	target/riscv: Add fw_dynamic_info32 for booting RV32 OpenSBI	9 months ago
iommu.h	hw/riscv/riscv-iommu: Remove definition of RISCVIOMMU[Pci|Sys]Class	1 month ago
microchip_pfsoc.h	hw/riscv: Configurable MPFS CLINT timebase freq	2 months ago
numa.h	include: Rename sysemu/ -> system/	7 months ago
opentitan.h	hw/riscv/opentitan: Correct OpenTitanState parent type/size	2 years ago
riscv_hart.h	target/riscv: Handle Smrnmi interrupt and exception	6 months ago
shakti_c.h	hw/intc: sifive_plic: Change "priority-base" to start from interrupt source 0	3 years ago
sifive_cpu.h	…
sifive_e.h	hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b.	2 years ago
sifive_u.h	hw/riscv: Move the dtb load bits outside of create_fdt()	2 years ago
spike.h	hw/riscv/spike: use 'fdt' from MachineState	3 years ago
virt.h	hw/riscv/virt: Add the BDF of IOMMU to RISCVVirtState structure	2 months ago
xiangshan_kmh.h	hw/riscv: Initial support for BOSC's Xiangshan Kunminghu FPGA prototype	2 weeks ago