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65 lines
1.6 KiB
C
65 lines
1.6 KiB
C
/*
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* Cluster Power Controller emulation
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*
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* Copyright (c) 2016 Imagination Technologies
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*
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* Copyright (c) 2025 MIPS
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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*/
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#ifndef RISCV_CPC_H
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#define RISCV_CPC_H
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#include "hw/core/sysbus.h"
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#include "qom/object.h"
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#define CPC_ADDRSPACE_SZ 0x6000
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/* CPC global register offsets relative to base address */
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#define CPC_MTIME_REG_OFS 0x50
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#define CPC_CM_STAT_CONF_OFS 0x1008
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/* CPC blocks offsets relative to base address */
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#define CPC_CL_BASE_OFS 0x2000
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#define CPC_CORE_REG_STRIDE 0x100 /* Stride between core-specific registers */
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/* CPC register offsets relative to block offsets */
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#define CPC_STAT_CONF_OFS 0x08
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#define CPC_VP_STOP_OFS 0x20
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#define CPC_VP_RUN_OFS 0x28
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#define CPC_VP_RUNNING_OFS 0x30
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#define SEQ_STATE_BIT 19
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#define SEQ_STATE_U5 0x6
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#define SEQ_STATE_U6 0x7
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U5 (SEQ_STATE_U5 << SEQ_STATE_BIT)
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#define CPC_Cx_STAT_CONF_SEQ_STATE_U6 (SEQ_STATE_U6 << SEQ_STATE_BIT)
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#define TYPE_RISCV_CPC "xmips-cpc"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVCPCState, RISCV_CPC)
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typedef struct RISCVCPCState {
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SysBusDevice parent_obj;
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uint32_t cluster_id;
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uint32_t num_vp;
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uint32_t num_hart;
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uint32_t num_core;
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/* VPs running from restart mask */
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uint64_t vps_start_running_mask;
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MemoryRegion mr;
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/* Indicates which VPs are in the run state mask */
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uint64_t vps_running_mask;
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/* Array of CPUs managed by this CPC */
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CPUState **cpus;
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} RISCVCPCState;
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#define CPC_MAX_VPS 64 /* Maximum number of VPs supported */
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#endif /* RISCV_CPC_H */
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