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49 lines
954 B
C
49 lines
954 B
C
/*
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* Coherent Manager Global Control Register
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*
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* Copyright (C) 2015 Imagination Technologies
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*
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* Copyright (C) 2025 MIPS
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*
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*/
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#ifndef RISCV_CMGCR_H
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#define RISCV_CMGCR_H
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#include "hw/core/sysbus.h"
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#include "qom/object.h"
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#define TYPE_RISCV_GCR "riscv-gcr"
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OBJECT_DECLARE_SIMPLE_TYPE(RISCVGCRState, RISCV_GCR)
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#define GCR_BASE_ADDR 0x1fb80000ULL
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#define GCR_MAX_VPS 256
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typedef struct RISCVGCRVPState RISCVGCRVPState;
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struct RISCVGCRVPState {
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uint64_t reset_base;
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};
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typedef struct RISCVGCRState RISCVGCRState;
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struct RISCVGCRState {
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SysBusDevice parent_obj;
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int32_t gcr_rev;
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uint32_t cluster_id;
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uint32_t num_vps;
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uint32_t num_hart;
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uint32_t num_core;
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hwaddr gcr_base;
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MemoryRegion iomem;
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MemoryRegion *cpc_mr;
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uint64_t cpc_base;
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/* VP Local/Other Registers */
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RISCVGCRVPState *vps;
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};
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#endif /* RISCV_CMGCR_H */
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