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132 lines
2.6 KiB
C
132 lines
2.6 KiB
C
/*
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* MAX78000 Global Control Register
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*
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* Copyright (c) 2025 Jackson Donaldson <jcksn@duck.com>
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HW_MAX78000_GCR_H
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#define HW_MAX78000_GCR_H
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#include "hw/sysbus.h"
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#include "qom/object.h"
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#define TYPE_MAX78000_GCR "max78000-gcr"
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OBJECT_DECLARE_SIMPLE_TYPE(Max78000GcrState, MAX78000_GCR)
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#define SYSCTRL 0x0
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#define RST0 0x4
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#define CLKCTRL 0x8
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#define PM 0xc
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#define PCLKDIV 0x18
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#define PCLKDIS0 0x24
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#define MEMCTRL 0x28
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#define MEMZ 0x2c
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#define SYSST 0x40
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#define RST1 0x44
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#define PCKDIS1 0x48
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#define EVENTEN 0x4c
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#define REVISION 0x50
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#define SYSIE 0x54
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#define ECCERR 0x64
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#define ECCED 0x68
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#define ECCIE 0x6c
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#define ECCADDR 0x70
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/* RST0 */
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#define SYSTEM_RESET (1 << 31)
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#define PERIPHERAL_RESET (1 << 30)
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#define SOFT_RESET (1 << 29)
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#define UART2_RESET (1 << 28)
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#define ADC_RESET (1 << 26)
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#define CNN_RESET (1 << 25)
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#define TRNG_RESET (1 << 24)
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#define RTC_RESET (1 << 17)
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#define I2C0_RESET (1 << 16)
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#define SPI1_RESET (1 << 13)
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#define UART1_RESET (1 << 12)
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#define UART0_RESET (1 << 11)
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#define TMR3_RESET (1 << 8)
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#define TMR2_RESET (1 << 7)
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#define TMR1_RESET (1 << 6)
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#define TMR0_RESET (1 << 5)
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#define GPIO1_RESET (1 << 3)
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#define GPIO0_RESET (1 << 2)
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#define WDT0_RESET (1 << 1)
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#define DMA_RESET (1 << 0)
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/* CLKCTRL */
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#define SYSCLK_RDY (1 << 13)
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/* MEMZ */
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#define ram0 (1 << 0)
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#define ram1 (1 << 1)
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#define ram2 (1 << 2)
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#define ram3 (1 << 3)
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/* RST1 */
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#define CPU1_RESET (1 << 31)
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#define SIMO_RESET (1 << 25)
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#define DVS_RESET (1 << 24)
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#define I2C2_RESET (1 << 20)
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#define I2S_RESET (1 << 19)
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#define SMPHR_RESET (1 << 16)
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#define SPI0_RESET (1 << 11)
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#define AES_RESET (1 << 10)
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#define CRC_RESET (1 << 9)
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#define PT_RESET (1 << 1)
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#define I2C1_RESET (1 << 0)
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#define SYSRAM0_START 0x20000000
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#define SYSRAM1_START 0x20008000
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#define SYSRAM2_START 0x20010000
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#define SYSRAM3_START 0x2001C000
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struct Max78000GcrState {
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SysBusDevice parent_obj;
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MemoryRegion mmio;
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uint32_t sysctrl;
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uint32_t rst0;
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uint32_t clkctrl;
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uint32_t pm;
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uint32_t pclkdiv;
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uint32_t pclkdis0;
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uint32_t memctrl;
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uint32_t memz;
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uint32_t sysst;
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uint32_t rst1;
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uint32_t pckdis1;
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uint32_t eventen;
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uint32_t revision;
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uint32_t sysie;
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uint32_t eccerr;
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uint32_t ecced;
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uint32_t eccie;
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uint32_t eccaddr;
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MemoryRegion *sram;
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AddressSpace sram_as;
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DeviceState *uart0;
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DeviceState *uart1;
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DeviceState *uart2;
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DeviceState *trng;
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DeviceState *aes;
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};
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#endif
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