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564 lines
16 KiB
C
564 lines
16 KiB
C
/*
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* Software MMU support (per-target)
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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/*
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* Generate inline load/store functions for all MMU modes (typically
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* at least _user and _kernel) as well as _data versions, for all data
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* sizes.
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*
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* Used by target op helpers.
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*
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* The syntax for the accessors is:
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*
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* load: cpu_ld{sign}{size}{end}_{mmusuffix}(env, ptr)
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* cpu_ld{sign}{size}{end}_{mmusuffix}_ra(env, ptr, retaddr)
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* cpu_ld{sign}{size}{end}_mmuidx_ra(env, ptr, mmu_idx, retaddr)
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* cpu_ld{sign}{size}{end}_mmu(env, ptr, oi, retaddr)
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*
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* store: cpu_st{size}{end}_{mmusuffix}(env, ptr, val)
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* cpu_st{size}{end}_{mmusuffix}_ra(env, ptr, val, retaddr)
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* cpu_st{size}{end}_mmuidx_ra(env, ptr, val, mmu_idx, retaddr)
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* cpu_st{size}{end}_mmu(env, ptr, val, oi, retaddr)
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*
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* sign is:
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* (empty): for 32 and 64 bit sizes
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* u : unsigned
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* s : signed
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*
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* size is:
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* b: 8 bits
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* w: 16 bits
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* l: 32 bits
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* q: 64 bits
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*
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* end is:
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* (empty): for target native endian, or for 8 bit access
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* _be: for forced big endian
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* _le: for forced little endian
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*
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* mmusuffix is one of the generic suffixes "data" or "code", or "mmuidx".
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* The "mmuidx" suffix carries an extra mmu_idx argument that specifies
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* the index to use; the "data" and "code" suffixes take the index from
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* cpu_mmu_index().
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*
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* The "mmu" suffix carries the full MemOpIdx, with both mmu_idx and the
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* MemOp including alignment requirements. The alignment will be enforced.
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*/
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#ifndef ACCEL_TCG_CPU_LDST_H
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#define ACCEL_TCG_CPU_LDST_H
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#ifndef CONFIG_TCG
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#error Can only include this header with TCG
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#endif
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#include "exec/cpu-common.h"
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#include "accel/tcg/cpu-ldst-common.h"
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#include "accel/tcg/cpu-mmu-index.h"
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#include "exec/abi_ptr.h"
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#if defined(CONFIG_USER_ONLY)
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#include "user/guest-host.h"
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#endif /* CONFIG_USER_ONLY */
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static inline uint32_t
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cpu_ldub_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
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return cpu_ldb_mmu(env, addr, oi, ra);
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}
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static inline int
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cpu_ldsb_mmuidx_ra(CPUArchState *env, abi_ptr addr, int mmu_idx, uintptr_t ra)
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{
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return (int8_t)cpu_ldub_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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static inline uint32_t
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cpu_lduw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
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return cpu_ldw_mmu(env, addr, oi, ra);
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}
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static inline int
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cpu_ldsw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_be_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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static inline uint32_t
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cpu_ldl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
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return cpu_ldl_mmu(env, addr, oi, ra);
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}
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static inline uint64_t
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cpu_ldq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx);
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return cpu_ldq_mmu(env, addr, oi, ra);
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}
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static inline uint32_t
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cpu_lduw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
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return cpu_ldw_mmu(env, addr, oi, ra);
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}
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static inline int
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cpu_ldsw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_le_mmuidx_ra(env, addr, mmu_idx, ra);
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}
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static inline uint32_t
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cpu_ldl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
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return cpu_ldl_mmu(env, addr, oi, ra);
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}
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static inline uint64_t
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cpu_ldq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx);
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return cpu_ldq_mmu(env, addr, oi, ra);
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}
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static inline void
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cpu_stb_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_UB, mmu_idx);
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cpu_stb_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stw_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUW | MO_UNALN, mmu_idx);
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cpu_stw_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stl_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUL | MO_UNALN, mmu_idx);
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cpu_stl_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stq_be_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_BEUQ | MO_UNALN, mmu_idx);
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cpu_stq_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stw_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUW | MO_UNALN, mmu_idx);
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cpu_stw_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stl_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint32_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUL | MO_UNALN, mmu_idx);
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cpu_stl_mmu(env, addr, val, oi, ra);
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}
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static inline void
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cpu_stq_le_mmuidx_ra(CPUArchState *env, abi_ptr addr, uint64_t val,
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int mmu_idx, uintptr_t ra)
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{
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MemOpIdx oi = make_memop_idx(MO_LEUQ | MO_UNALN, mmu_idx);
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cpu_stq_mmu(env, addr, val, oi, ra);
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}
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/*--------------------------*/
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static inline uint32_t
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cpu_ldub_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_ldub_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline int
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cpu_ldsb_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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return (int8_t)cpu_ldub_data_ra(env, addr, ra);
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}
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static inline uint32_t
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cpu_lduw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_lduw_be_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline int
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cpu_ldsw_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_be_data_ra(env, addr, ra);
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}
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static inline uint32_t
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cpu_ldl_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_ldl_be_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline uint64_t
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cpu_ldq_be_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_ldq_be_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline uint32_t
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cpu_lduw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_lduw_le_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline int
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cpu_ldsw_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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return (int16_t)cpu_lduw_le_data_ra(env, addr, ra);
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}
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static inline uint32_t
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cpu_ldl_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_ldl_le_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline uint64_t
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cpu_ldq_le_data_ra(CPUArchState *env, abi_ptr addr, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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return cpu_ldq_le_mmuidx_ra(env, addr, mmu_index, ra);
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}
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static inline void
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cpu_stb_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stb_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stw_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stw_be_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stl_be_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stl_be_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stq_be_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stq_be_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stw_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stw_le_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stl_le_data_ra(CPUArchState *env, abi_ptr addr, uint32_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stl_le_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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static inline void
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cpu_stq_le_data_ra(CPUArchState *env, abi_ptr addr, uint64_t val, uintptr_t ra)
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{
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int mmu_index = cpu_mmu_index(env_cpu(env), false);
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cpu_stq_le_mmuidx_ra(env, addr, val, mmu_index, ra);
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}
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/*--------------------------*/
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static inline uint32_t
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cpu_ldub_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_ldub_data_ra(env, addr, 0);
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}
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static inline int
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cpu_ldsb_data(CPUArchState *env, abi_ptr addr)
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{
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return (int8_t)cpu_ldub_data(env, addr);
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}
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static inline uint32_t
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cpu_lduw_be_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_lduw_be_data_ra(env, addr, 0);
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}
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static inline int
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cpu_ldsw_be_data(CPUArchState *env, abi_ptr addr)
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{
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return (int16_t)cpu_lduw_be_data(env, addr);
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}
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static inline uint32_t
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cpu_ldl_be_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_ldl_be_data_ra(env, addr, 0);
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}
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static inline uint64_t
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cpu_ldq_be_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_ldq_be_data_ra(env, addr, 0);
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}
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static inline uint32_t
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cpu_lduw_le_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_lduw_le_data_ra(env, addr, 0);
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}
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static inline int
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cpu_ldsw_le_data(CPUArchState *env, abi_ptr addr)
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{
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return (int16_t)cpu_lduw_le_data(env, addr);
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}
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static inline uint32_t
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cpu_ldl_le_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_ldl_le_data_ra(env, addr, 0);
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}
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static inline uint64_t
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cpu_ldq_le_data(CPUArchState *env, abi_ptr addr)
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{
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return cpu_ldq_le_data_ra(env, addr, 0);
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}
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static inline void
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cpu_stb_data(CPUArchState *env, abi_ptr addr, uint32_t val)
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{
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cpu_stb_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stw_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
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{
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cpu_stw_be_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stl_be_data(CPUArchState *env, abi_ptr addr, uint32_t val)
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{
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cpu_stl_be_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stq_be_data(CPUArchState *env, abi_ptr addr, uint64_t val)
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{
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cpu_stq_be_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stw_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
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{
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cpu_stw_le_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stl_le_data(CPUArchState *env, abi_ptr addr, uint32_t val)
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{
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cpu_stl_le_data_ra(env, addr, val, 0);
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}
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static inline void
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cpu_stq_le_data(CPUArchState *env, abi_ptr addr, uint64_t val)
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{
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cpu_stq_le_data_ra(env, addr, val, 0);
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}
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#if TARGET_BIG_ENDIAN
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# define cpu_lduw_data cpu_lduw_be_data
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# define cpu_ldsw_data cpu_ldsw_be_data
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# define cpu_ldl_data cpu_ldl_be_data
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# define cpu_ldq_data cpu_ldq_be_data
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# define cpu_lduw_data_ra cpu_lduw_be_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_be_data_ra
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# define cpu_ldl_data_ra cpu_ldl_be_data_ra
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# define cpu_ldq_data_ra cpu_ldq_be_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_be_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_be_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_be_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_be_mmuidx_ra
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# define cpu_stw_data cpu_stw_be_data
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# define cpu_stl_data cpu_stl_be_data
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# define cpu_stq_data cpu_stq_be_data
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# define cpu_stw_data_ra cpu_stw_be_data_ra
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# define cpu_stl_data_ra cpu_stl_be_data_ra
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# define cpu_stq_data_ra cpu_stq_be_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_be_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_be_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_be_mmuidx_ra
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#else
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# define cpu_lduw_data cpu_lduw_le_data
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# define cpu_ldsw_data cpu_ldsw_le_data
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# define cpu_ldl_data cpu_ldl_le_data
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# define cpu_ldq_data cpu_ldq_le_data
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# define cpu_lduw_data_ra cpu_lduw_le_data_ra
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# define cpu_ldsw_data_ra cpu_ldsw_le_data_ra
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# define cpu_ldl_data_ra cpu_ldl_le_data_ra
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# define cpu_ldq_data_ra cpu_ldq_le_data_ra
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# define cpu_lduw_mmuidx_ra cpu_lduw_le_mmuidx_ra
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# define cpu_ldsw_mmuidx_ra cpu_ldsw_le_mmuidx_ra
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# define cpu_ldl_mmuidx_ra cpu_ldl_le_mmuidx_ra
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# define cpu_ldq_mmuidx_ra cpu_ldq_le_mmuidx_ra
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# define cpu_stw_data cpu_stw_le_data
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# define cpu_stl_data cpu_stl_le_data
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# define cpu_stq_data cpu_stq_le_data
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# define cpu_stw_data_ra cpu_stw_le_data_ra
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# define cpu_stl_data_ra cpu_stl_le_data_ra
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# define cpu_stq_data_ra cpu_stq_le_data_ra
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# define cpu_stw_mmuidx_ra cpu_stw_le_mmuidx_ra
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# define cpu_stl_mmuidx_ra cpu_stl_le_mmuidx_ra
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# define cpu_stq_mmuidx_ra cpu_stq_le_mmuidx_ra
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#endif
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static inline uint32_t cpu_ldub_code(CPUArchState *env, abi_ptr addr)
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{
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CPUState *cs = env_cpu(env);
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MemOpIdx oi = make_memop_idx(MO_UB, cpu_mmu_index(cs, true));
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return cpu_ldb_code_mmu(env, addr, oi, 0);
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}
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static inline uint32_t cpu_lduw_code(CPUArchState *env, abi_ptr addr)
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{
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CPUState *cs = env_cpu(env);
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MemOpIdx oi = make_memop_idx(MO_TEUW, cpu_mmu_index(cs, true));
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return cpu_ldw_code_mmu(env, addr, oi, 0);
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}
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static inline uint32_t cpu_ldl_code(CPUArchState *env, abi_ptr addr)
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{
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CPUState *cs = env_cpu(env);
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MemOpIdx oi = make_memop_idx(MO_TEUL, cpu_mmu_index(cs, true));
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return cpu_ldl_code_mmu(env, addr, oi, 0);
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}
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static inline uint64_t cpu_ldq_code(CPUArchState *env, abi_ptr addr)
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{
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CPUState *cs = env_cpu(env);
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MemOpIdx oi = make_memop_idx(MO_TEUQ, cpu_mmu_index(cs, true));
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return cpu_ldq_code_mmu(env, addr, oi, 0);
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}
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/**
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* tlb_vaddr_to_host:
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* @env: CPUArchState
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* @addr: guest virtual address to look up
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* @access_type: 0 for read, 1 for write, 2 for execute
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* @mmu_idx: MMU index to use for lookup
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*
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* Look up the specified guest virtual index in the TCG softmmu TLB.
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* If we can translate a host virtual address suitable for direct RAM
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* access, without causing a guest exception, then return it.
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* Otherwise (TLB entry is for an I/O access, guest software
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* TLB fill required, etc) return NULL.
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*/
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#ifdef CONFIG_USER_ONLY
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static inline void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr,
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MMUAccessType access_type, int mmu_idx)
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{
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return g2h(env_cpu(env), addr);
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}
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#else
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void *tlb_vaddr_to_host(CPUArchState *env, vaddr addr,
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MMUAccessType access_type, int mmu_idx);
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#endif
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/*
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* For user-only, helpers that use guest to host address translation
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|
* must protect the actual host memory access by recording 'retaddr'
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|
* for the signal handler. This is required for a race condition in
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* which another thread unmaps the page between a probe and the
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* actual access.
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*/
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#ifdef CONFIG_USER_ONLY
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extern __thread uintptr_t helper_retaddr;
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static inline void set_helper_retaddr(uintptr_t ra)
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|
{
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|
helper_retaddr = ra;
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|
/*
|
|
* Ensure that this write is visible to the SIGSEGV handler that
|
|
* may be invoked due to a subsequent invalid memory operation.
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|
*/
|
|
signal_barrier();
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|
}
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|
|
|
static inline void clear_helper_retaddr(void)
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|
{
|
|
/*
|
|
* Ensure that previous memory operations have succeeded before
|
|
* removing the data visible to the signal handler.
|
|
*/
|
|
signal_barrier();
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|
helper_retaddr = 0;
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|
}
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|
#else
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#define set_helper_retaddr(ra) do { } while (0)
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#define clear_helper_retaddr() do { } while (0)
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|
#endif
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#endif /* ACCEL_TCG_CPU_LDST_H */
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