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${ noResults }
Richard Henderson
981f2beb16
target: Use cpu_pointer_wrap_uint32 for 32-bit targets
M68K, MicroBlaze, OpenRISC, RX, TriCore and Xtensa are all 32-bit targets. AVR is more complicated, but using a 32-bit wrap preserves current behaviour. Cc: Michael Rolnik <mrolnik@gmail.com> Cc: Laurent Vivier <laurent@vivier.eu> Cc: Stafford Horne <shorne@gmail.com> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Max Filippov <jcmvbkbc@gmail.com> Tested-by Bastian Koppelmann <kbastian@mail.uni-paderborn.de> (tricore) Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> |
1 month ago | |
|---|---|---|
| .. | ||
| cpu-ldst-common.h | exec: Restrict 'cpu-ldst-common.h' to accel/tcg/ | 2 months ago |
| cpu-ldst.h | accel/tcg: Move tlb_vaddr_to_host declaration to probe.h | 2 months ago |
| cpu-mmu-index.h | hw/core/cpu: Remove CPUClass::mmu_index() | 2 months ago |
| cpu-ops.h | target: Use cpu_pointer_wrap_uint32 for 32-bit targets | 1 month ago |
| getpc.h | accel/tcg: Remove #error for non-tcg in getpc.h | 2 months ago |
| helper-retaddr.h | accel/tcg: Split out accel/tcg/helper-retaddr.h | 2 months ago |
| iommu.h | physmem: Restrict TCG IOTLB code to TCG accel | 2 months ago |
| probe.h | accel/tcg: Move tlb_vaddr_to_host declaration to probe.h | 2 months ago |
| tb-cpu-state.h | accel/tcg: Return TCGTBCPUState from cpu_get_tb_cpu_state | 2 months ago |