cpu_pgxp.h (3288B)
1 // SPDX-FileCopyrightText: 2016 iCatButler, 2019-2023 Connor McLaughlin <stenzek@gmail.com> 2 // SPDX-License-Identifier: GPL-2.0+ 3 4 #pragma once 5 #include "cpu_core.h" 6 7 namespace CPU::PGXP { 8 9 /// State management. 10 void Initialize(); 11 void Reset(); 12 void Shutdown(); 13 14 /// Vertex lookup from GPU side. 15 bool GetPreciseVertex(u32 addr, u32 value, int x, int y, int xOffs, int yOffs, float* out_x, float* out_y, 16 float* out_w); 17 18 // GTE instruction hooks. 19 20 void GTE_RTPS(float x, float y, float z, u32 value); 21 bool GTE_HasPreciseVertices(u32 sxy0, u32 sxy1, u32 sxy2); 22 float GTE_NCLIP(); 23 24 // CPU instruction implementations. 25 26 void CPU_MFC2(Instruction instr, u32 rdVal); 27 void CPU_MTC2(Instruction instr, u32 rtVal); 28 void CPU_LWC2(Instruction instr, u32 addr, u32 rtVal); 29 void CPU_SWC2(Instruction instr, u32 addr, u32 rtVal); 30 void CPU_LW(Instruction instr, u32 addr, u32 rtVal); 31 void CPU_LH(Instruction instr, u32 addr, u32 rtVal); 32 void CPU_LHU(Instruction instr, u32 addr, u32 rtVal); 33 void CPU_LBx(Instruction instr, u32 addr, u32 rtVal); 34 void CPU_SB(Instruction instr, u32 addr, u32 rtVal); 35 void CPU_SH(Instruction instr, u32 addr, u32 rtVal); 36 void CPU_SW(Instruction instr, u32 addr, u32 rtVal); 37 void CPU_MOVE(u32 Rd, u32 Rs, u32 rsVal); 38 void CPU_MOVE_Packed(u32 rd_and_rs, u32 rsVal); 39 void CPU_ADDI(Instruction instr, u32 rsVal); 40 void CPU_ANDI(Instruction instr, u32 rsVal); 41 void CPU_ORI(Instruction instr, u32 rsVal); 42 void CPU_XORI(Instruction instr, u32 rsVal); 43 void CPU_SLTI(Instruction instr, u32 rsVal); 44 void CPU_SLTIU(Instruction instr, u32 rsVal); 45 void CPU_LUI(Instruction instr); 46 void CPU_ADD(Instruction instr, u32 rsVal, u32 rtVal); 47 void CPU_SUB(Instruction instr, u32 rsVal, u32 rtVal); 48 void CPU_AND_(Instruction instr, u32 rsVal, u32 rtVal); 49 void CPU_OR_(Instruction instr, u32 rsVal, u32 rtVal); 50 void CPU_XOR_(Instruction instr, u32 rsVal, u32 rtVal); 51 void CPU_NOR(Instruction instr, u32 rsVal, u32 rtVal); 52 void CPU_SLT(Instruction instr, u32 rsVal, u32 rtVal); 53 void CPU_SLTU(Instruction instr, u32 rsVal, u32 rtVal); 54 void CPU_MULT(Instruction instr, u32 rsVal, u32 rtVal); 55 void CPU_MULTU(Instruction instr, u32 rsVal, u32 rtVal); 56 void CPU_DIV(Instruction instr, u32 rsVal, u32 rtVal); 57 void CPU_DIVU(Instruction instr, u32 rsVal, u32 rtVal); 58 void CPU_SLL(Instruction instr, u32 rtVal); 59 void CPU_SRL(Instruction instr, u32 rtVal); 60 void CPU_SRA(Instruction instr, u32 rtVal); 61 void CPU_SLLV(Instruction instr, u32 rtVal, u32 rsVal); 62 void CPU_SRLV(Instruction instr, u32 rtVal, u32 rsVal); 63 void CPU_SRAV(Instruction instr, u32 rtVal, u32 rsVal); 64 void CPU_MFC0(Instruction instr, u32 rdVal); 65 void CPU_MTC0(Instruction instr, u32 rdVal, u32 rtVal); 66 67 // Utility functions. 68 69 ALWAYS_INLINE static u32 PackMoveArgs(Reg rd, Reg rs) 70 { 71 return (static_cast<u32>(rd) << 8) | static_cast<u32>(rs); 72 } 73 74 ALWAYS_INLINE void TryMove(Reg rd, Reg rs, Reg rt) 75 { 76 u32 src; 77 if (rs == Reg::zero) 78 src = static_cast<u32>(rt); 79 else if (rt == Reg::zero) 80 src = static_cast<u32>(rs); 81 else 82 return; 83 84 CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]); 85 } 86 87 ALWAYS_INLINE void TryMoveImm(Reg rd, Reg rs, u32 imm) 88 { 89 if (imm == 0) 90 { 91 const u32 src = static_cast<u32>(rs); 92 CPU_MOVE(static_cast<u32>(rd), src, g_state.regs.r[src]); 93 } 94 } 95 96 } // namespace CPU::PGXP