riscv-disas.h (9883B)
1 /* 2 * RISC-V Disassembler 3 * 4 * Copyright (c) 2016-2017 Michael Clark <michaeljclark@mac.com> 5 * Copyright (c) 2017-2018 SiFive, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #ifndef RISCV_DISASSEMBLER_H 27 #define RISCV_DISASSEMBLER_H 28 29 #include <stdio.h> 30 #include <stdlib.h> 31 #include <stdint.h> 32 #include <stdbool.h> 33 #include <inttypes.h> 34 #include <string.h> 35 36 /* types */ 37 38 typedef uint64_t rv_inst; 39 typedef uint16_t rv_opcode; 40 41 /* enums */ 42 43 typedef enum { 44 rv32, 45 rv64, 46 rv128 47 } rv_isa; 48 49 typedef enum { 50 rv_rm_rne = 0, 51 rv_rm_rtz = 1, 52 rv_rm_rdn = 2, 53 rv_rm_rup = 3, 54 rv_rm_rmm = 4, 55 rv_rm_dyn = 7, 56 } rv_rm; 57 58 typedef enum { 59 rv_fence_i = 8, 60 rv_fence_o = 4, 61 rv_fence_r = 2, 62 rv_fence_w = 1, 63 } rv_fence; 64 65 typedef enum { 66 rv_ireg_zero, 67 rv_ireg_ra, 68 rv_ireg_sp, 69 rv_ireg_gp, 70 rv_ireg_tp, 71 rv_ireg_t0, 72 rv_ireg_t1, 73 rv_ireg_t2, 74 rv_ireg_s0, 75 rv_ireg_s1, 76 rv_ireg_a0, 77 rv_ireg_a1, 78 rv_ireg_a2, 79 rv_ireg_a3, 80 rv_ireg_a4, 81 rv_ireg_a5, 82 rv_ireg_a6, 83 rv_ireg_a7, 84 rv_ireg_s2, 85 rv_ireg_s3, 86 rv_ireg_s4, 87 rv_ireg_s5, 88 rv_ireg_s6, 89 rv_ireg_s7, 90 rv_ireg_s8, 91 rv_ireg_s9, 92 rv_ireg_s10, 93 rv_ireg_s11, 94 rv_ireg_t3, 95 rv_ireg_t4, 96 rv_ireg_t5, 97 rv_ireg_t6, 98 } rv_ireg; 99 100 typedef enum { 101 rvc_end, 102 rvc_rd_eq_ra, 103 rvc_rd_eq_x0, 104 rvc_rs1_eq_x0, 105 rvc_rs2_eq_x0, 106 rvc_rs2_eq_rs1, 107 rvc_rs1_eq_ra, 108 rvc_imm_eq_zero, 109 rvc_imm_eq_n1, 110 rvc_imm_eq_p1, 111 rvc_csr_eq_0x001, 112 rvc_csr_eq_0x002, 113 rvc_csr_eq_0x003, 114 rvc_csr_eq_0xc00, 115 rvc_csr_eq_0xc01, 116 rvc_csr_eq_0xc02, 117 rvc_csr_eq_0xc80, 118 rvc_csr_eq_0xc81, 119 rvc_csr_eq_0xc82, 120 } rvc_constraint; 121 122 typedef enum { 123 rv_codec_illegal, 124 rv_codec_none, 125 rv_codec_u, 126 rv_codec_uj, 127 rv_codec_i, 128 rv_codec_i_sh5, 129 rv_codec_i_sh6, 130 rv_codec_i_sh7, 131 rv_codec_i_csr, 132 rv_codec_s, 133 rv_codec_sb, 134 rv_codec_r, 135 rv_codec_r_m, 136 rv_codec_r4_m, 137 rv_codec_r_a, 138 rv_codec_r_l, 139 rv_codec_r_f, 140 rv_codec_cb, 141 rv_codec_cb_imm, 142 rv_codec_cb_sh5, 143 rv_codec_cb_sh6, 144 rv_codec_ci, 145 rv_codec_ci_sh5, 146 rv_codec_ci_sh6, 147 rv_codec_ci_16sp, 148 rv_codec_ci_lwsp, 149 rv_codec_ci_ldsp, 150 rv_codec_ci_lqsp, 151 rv_codec_ci_li, 152 rv_codec_ci_lui, 153 rv_codec_ci_none, 154 rv_codec_ciw_4spn, 155 rv_codec_cj, 156 rv_codec_cj_jal, 157 rv_codec_cl_lw, 158 rv_codec_cl_ld, 159 rv_codec_cl_lq, 160 rv_codec_cr, 161 rv_codec_cr_mv, 162 rv_codec_cr_jalr, 163 rv_codec_cr_jr, 164 rv_codec_cs, 165 rv_codec_cs_sw, 166 rv_codec_cs_sd, 167 rv_codec_cs_sq, 168 rv_codec_css_swsp, 169 rv_codec_css_sdsp, 170 rv_codec_css_sqsp, 171 } rv_codec; 172 173 typedef enum { 174 rv_op_illegal, 175 rv_op_lui, 176 rv_op_auipc, 177 rv_op_jal, 178 rv_op_jalr, 179 rv_op_beq, 180 rv_op_bne, 181 rv_op_blt, 182 rv_op_bge, 183 rv_op_bltu, 184 rv_op_bgeu, 185 rv_op_lb, 186 rv_op_lh, 187 rv_op_lw, 188 rv_op_lbu, 189 rv_op_lhu, 190 rv_op_sb, 191 rv_op_sh, 192 rv_op_sw, 193 rv_op_addi, 194 rv_op_slti, 195 rv_op_sltiu, 196 rv_op_xori, 197 rv_op_ori, 198 rv_op_andi, 199 rv_op_slli, 200 rv_op_srli, 201 rv_op_srai, 202 rv_op_add, 203 rv_op_sub, 204 rv_op_sll, 205 rv_op_slt, 206 rv_op_sltu, 207 rv_op_xor, 208 rv_op_srl, 209 rv_op_sra, 210 rv_op_or, 211 rv_op_and, 212 rv_op_fence, 213 rv_op_fence_i, 214 rv_op_lwu, 215 rv_op_ld, 216 rv_op_sd, 217 rv_op_addiw, 218 rv_op_slliw, 219 rv_op_srliw, 220 rv_op_sraiw, 221 rv_op_addw, 222 rv_op_subw, 223 rv_op_sllw, 224 rv_op_srlw, 225 rv_op_sraw, 226 rv_op_ldu, 227 rv_op_lq, 228 rv_op_sq, 229 rv_op_addid, 230 rv_op_sllid, 231 rv_op_srlid, 232 rv_op_sraid, 233 rv_op_addd, 234 rv_op_subd, 235 rv_op_slld, 236 rv_op_srld, 237 rv_op_srad, 238 rv_op_mul, 239 rv_op_mulh, 240 rv_op_mulhsu, 241 rv_op_mulhu, 242 rv_op_div, 243 rv_op_divu, 244 rv_op_rem, 245 rv_op_remu, 246 rv_op_mulw, 247 rv_op_divw, 248 rv_op_divuw, 249 rv_op_remw, 250 rv_op_remuw, 251 rv_op_muld, 252 rv_op_divd, 253 rv_op_divud, 254 rv_op_remd, 255 rv_op_remud, 256 rv_op_lr_w, 257 rv_op_sc_w, 258 rv_op_amoswap_w, 259 rv_op_amoadd_w, 260 rv_op_amoxor_w, 261 rv_op_amoor_w, 262 rv_op_amoand_w, 263 rv_op_amomin_w, 264 rv_op_amomax_w, 265 rv_op_amominu_w, 266 rv_op_amomaxu_w, 267 rv_op_lr_d, 268 rv_op_sc_d, 269 rv_op_amoswap_d, 270 rv_op_amoadd_d, 271 rv_op_amoxor_d, 272 rv_op_amoor_d, 273 rv_op_amoand_d, 274 rv_op_amomin_d, 275 rv_op_amomax_d, 276 rv_op_amominu_d, 277 rv_op_amomaxu_d, 278 rv_op_lr_q, 279 rv_op_sc_q, 280 rv_op_amoswap_q, 281 rv_op_amoadd_q, 282 rv_op_amoxor_q, 283 rv_op_amoor_q, 284 rv_op_amoand_q, 285 rv_op_amomin_q, 286 rv_op_amomax_q, 287 rv_op_amominu_q, 288 rv_op_amomaxu_q, 289 rv_op_ecall, 290 rv_op_ebreak, 291 rv_op_uret, 292 rv_op_sret, 293 rv_op_hret, 294 rv_op_mret, 295 rv_op_dret, 296 rv_op_sfence_vm, 297 rv_op_sfence_vma, 298 rv_op_wfi, 299 rv_op_csrrw, 300 rv_op_csrrs, 301 rv_op_csrrc, 302 rv_op_csrrwi, 303 rv_op_csrrsi, 304 rv_op_csrrci, 305 rv_op_flw, 306 rv_op_fsw, 307 rv_op_fmadd_s, 308 rv_op_fmsub_s, 309 rv_op_fnmsub_s, 310 rv_op_fnmadd_s, 311 rv_op_fadd_s, 312 rv_op_fsub_s, 313 rv_op_fmul_s, 314 rv_op_fdiv_s, 315 rv_op_fsgnj_s, 316 rv_op_fsgnjn_s, 317 rv_op_fsgnjx_s, 318 rv_op_fmin_s, 319 rv_op_fmax_s, 320 rv_op_fsqrt_s, 321 rv_op_fle_s, 322 rv_op_flt_s, 323 rv_op_feq_s, 324 rv_op_fcvt_w_s, 325 rv_op_fcvt_wu_s, 326 rv_op_fcvt_s_w, 327 rv_op_fcvt_s_wu, 328 rv_op_fmv_x_s, 329 rv_op_fclass_s, 330 rv_op_fmv_s_x, 331 rv_op_fcvt_l_s, 332 rv_op_fcvt_lu_s, 333 rv_op_fcvt_s_l, 334 rv_op_fcvt_s_lu, 335 rv_op_fld, 336 rv_op_fsd, 337 rv_op_fmadd_d, 338 rv_op_fmsub_d, 339 rv_op_fnmsub_d, 340 rv_op_fnmadd_d, 341 rv_op_fadd_d, 342 rv_op_fsub_d, 343 rv_op_fmul_d, 344 rv_op_fdiv_d, 345 rv_op_fsgnj_d, 346 rv_op_fsgnjn_d, 347 rv_op_fsgnjx_d, 348 rv_op_fmin_d, 349 rv_op_fmax_d, 350 rv_op_fcvt_s_d, 351 rv_op_fcvt_d_s, 352 rv_op_fsqrt_d, 353 rv_op_fle_d, 354 rv_op_flt_d, 355 rv_op_feq_d, 356 rv_op_fcvt_w_d, 357 rv_op_fcvt_wu_d, 358 rv_op_fcvt_d_w, 359 rv_op_fcvt_d_wu, 360 rv_op_fclass_d, 361 rv_op_fcvt_l_d, 362 rv_op_fcvt_lu_d, 363 rv_op_fmv_x_d, 364 rv_op_fcvt_d_l, 365 rv_op_fcvt_d_lu, 366 rv_op_fmv_d_x, 367 rv_op_flq, 368 rv_op_fsq, 369 rv_op_fmadd_q, 370 rv_op_fmsub_q, 371 rv_op_fnmsub_q, 372 rv_op_fnmadd_q, 373 rv_op_fadd_q, 374 rv_op_fsub_q, 375 rv_op_fmul_q, 376 rv_op_fdiv_q, 377 rv_op_fsgnj_q, 378 rv_op_fsgnjn_q, 379 rv_op_fsgnjx_q, 380 rv_op_fmin_q, 381 rv_op_fmax_q, 382 rv_op_fcvt_s_q, 383 rv_op_fcvt_q_s, 384 rv_op_fcvt_d_q, 385 rv_op_fcvt_q_d, 386 rv_op_fsqrt_q, 387 rv_op_fle_q, 388 rv_op_flt_q, 389 rv_op_feq_q, 390 rv_op_fcvt_w_q, 391 rv_op_fcvt_wu_q, 392 rv_op_fcvt_q_w, 393 rv_op_fcvt_q_wu, 394 rv_op_fclass_q, 395 rv_op_fcvt_l_q, 396 rv_op_fcvt_lu_q, 397 rv_op_fcvt_q_l, 398 rv_op_fcvt_q_lu, 399 rv_op_fmv_x_q, 400 rv_op_fmv_q_x, 401 rv_op_c_addi4spn, 402 rv_op_c_fld, 403 rv_op_c_lw, 404 rv_op_c_flw, 405 rv_op_c_fsd, 406 rv_op_c_sw, 407 rv_op_c_fsw, 408 rv_op_c_nop, 409 rv_op_c_addi, 410 rv_op_c_jal, 411 rv_op_c_li, 412 rv_op_c_addi16sp, 413 rv_op_c_lui, 414 rv_op_c_srli, 415 rv_op_c_srai, 416 rv_op_c_andi, 417 rv_op_c_sub, 418 rv_op_c_xor, 419 rv_op_c_or, 420 rv_op_c_and, 421 rv_op_c_subw, 422 rv_op_c_addw, 423 rv_op_c_j, 424 rv_op_c_beqz, 425 rv_op_c_bnez, 426 rv_op_c_slli, 427 rv_op_c_fldsp, 428 rv_op_c_lwsp, 429 rv_op_c_flwsp, 430 rv_op_c_jr, 431 rv_op_c_mv, 432 rv_op_c_ebreak, 433 rv_op_c_jalr, 434 rv_op_c_add, 435 rv_op_c_fsdsp, 436 rv_op_c_swsp, 437 rv_op_c_fswsp, 438 rv_op_c_ld, 439 rv_op_c_sd, 440 rv_op_c_addiw, 441 rv_op_c_ldsp, 442 rv_op_c_sdsp, 443 rv_op_c_lq, 444 rv_op_c_sq, 445 rv_op_c_lqsp, 446 rv_op_c_sqsp, 447 rv_op_nop, 448 rv_op_mv, 449 rv_op_not, 450 rv_op_neg, 451 rv_op_negw, 452 rv_op_sext_w, 453 rv_op_seqz, 454 rv_op_snez, 455 rv_op_sltz, 456 rv_op_sgtz, 457 rv_op_fmv_s, 458 rv_op_fabs_s, 459 rv_op_fneg_s, 460 rv_op_fmv_d, 461 rv_op_fabs_d, 462 rv_op_fneg_d, 463 rv_op_fmv_q, 464 rv_op_fabs_q, 465 rv_op_fneg_q, 466 rv_op_beqz, 467 rv_op_bnez, 468 rv_op_blez, 469 rv_op_bgez, 470 rv_op_bltz, 471 rv_op_bgtz, 472 rv_op_ble, 473 rv_op_bleu, 474 rv_op_bgt, 475 rv_op_bgtu, 476 rv_op_j, 477 rv_op_ret, 478 rv_op_jr, 479 rv_op_rdcycle, 480 rv_op_rdtime, 481 rv_op_rdinstret, 482 rv_op_rdcycleh, 483 rv_op_rdtimeh, 484 rv_op_rdinstreth, 485 rv_op_frcsr, 486 rv_op_frrm, 487 rv_op_frflags, 488 rv_op_fscsr, 489 rv_op_fsrm, 490 rv_op_fsflags, 491 rv_op_fsrmi, 492 rv_op_fsflagsi, 493 } rv_op; 494 495 /* structures */ 496 497 typedef struct { 498 uint64_t pc; 499 uint64_t inst; 500 int32_t imm; 501 uint16_t op; 502 uint8_t codec; 503 uint8_t rd; 504 uint8_t rs1; 505 uint8_t rs2; 506 uint8_t rs3; 507 uint8_t rm; 508 uint8_t pred; 509 uint8_t succ; 510 uint8_t aq; 511 uint8_t rl; 512 } rv_decode; 513 514 /* functions */ 515 516 size_t inst_length(rv_inst inst); 517 void inst_fetch(const uint8_t *data, rv_inst *instp, size_t *length); 518 void disasm_inst(char *buf, size_t buflen, rv_isa isa, uint64_t pc, rv_inst inst); 519 520 #endif