waf_demo.xise (37759B)
1 <?xml version="1.0" encoding="UTF-8" standalone="no" ?> 2 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema"> 3 4 <header> 5 <!-- ISE source project file created by Project Navigator. --> 6 <!-- --> 7 <!-- This file contains project source information including a list of --> 8 <!-- project source files, project and process properties. This file, --> 9 <!-- along with the project source files, is sufficient to open and --> 10 <!-- implement in ISE Project Navigator. --> 11 <!-- --> 12 <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> 13 </header> 14 15 <version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/> 16 17 <files> 18 <file xil_pn:name="src/top.vhd" xil_pn:type="FILE_VHDL"> 19 <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> 20 <association xil_pn:name="Implementation" xil_pn:seqID="3"/> 21 </file> 22 <file xil_pn:name="src/rs1.ucf" xil_pn:type="FILE_UCF"> 23 <association xil_pn:name="Implementation" xil_pn:seqID="15"/> 24 </file> 25 </files> 26 27 <properties> 28 <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/> 29 <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/> 30 <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/> 31 <property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/> 32 <property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" 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xil_pn:valueState="default"/> 215 <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/> 216 <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="pci_7seg_map.vhd" xil_pn:valueState="default"/> 217 <property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="pci_7seg_timesim.vhd" xil_pn:valueState="default"/> 218 <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="pci_7seg_synthesis.vhd" xil_pn:valueState="default"/> 219 <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="pci_7seg_translate.vhd" xil_pn:valueState="default"/> 220 <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/> 221 <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/> 222 <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/> 223 <property xil_pn:name="Priority Encoder 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<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/> 234 <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/> 235 <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/> 236 <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/> 237 <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/> 238 <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/> 239 <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/> 240 <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/> 241 <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="pci_7seg" xil_pn:valueState="default"/> 242 <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/> 243 <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="false" xil_pn:valueState="non-default"/> 244 <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="false" xil_pn:valueState="non-default"/> 245 <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/> 246 <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> 247 <property xil_pn:name="Report Type" xil_pn:value="Error Report" xil_pn:valueState="non-default"/> 248 <property xil_pn:name="Report Type Post Trace" xil_pn:value="Error Report" xil_pn:valueState="non-default"/> 249 <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/> 250 <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/> 251 <property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/> 252 <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/> 253 <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/> 254 <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/> 255 <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/> 256 <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/> 257 <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/> 258 <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/> 259 <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/> 260 <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> 261 <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> 262 <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> 263 <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/> 264 <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> 265 <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> 266 <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> 267 <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/> 268 <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/> 269 <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/> 270 <property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/> 271 <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/> 272 <property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/> 273 <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/> 274 <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/> 275 <property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/> 276 <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/> 277 <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/> 278 <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> 279 <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/> 280 <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> 281 <property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/> 282 <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> 283 <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/> 284 <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> 285 <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> 286 <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> 287 <property xil_pn:name="Speed Grade" xil_pn:value="-4" xil_pn:valueState="non-default"/> 288 <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/> 289 <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> 290 <property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/> 291 <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> 292 <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> 293 <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/> 294 <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> 295 <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> 296 <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> 297 <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/> 298 <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> 299 <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> 300 <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> 301 <property xil_pn:name="Use Automatic Do File" xil_pn:value="true" xil_pn:valueState="default"/> 302 <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/> 303 <property xil_pn:name="Use Configuration Name" xil_pn:value="false" xil_pn:valueState="default"/> 304 <property xil_pn:name="Use Custom Do File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> 305 <property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/> 306 <property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/> 307 <property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/> 308 <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> 309 <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> 310 <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> 311 <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/> 312 <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> 313 <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/> 314 <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/> 315 <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/> 316 <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/> 317 <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/> 318 <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/> 319 <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/> 320 <property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/> 321 <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> 322 <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> 323 <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> 324 <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/> 325 <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/> 326 <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> 327 <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/> 328 <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> 329 <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> 330 <property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/> 331 <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/> 332 <property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/> 333 <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/> 334 <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/> 335 <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/> 336 <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/> 337 <property xil_pn:name="Wave window" xil_pn:value="true" xil_pn:valueState="default"/> 338 <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/> 339 <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/> 340 <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/> 341 <property xil_pn:name="iMPACT Project File" xil_pn:value="cJ_impact.ipf" xil_pn:valueState="non-default"/> 342 <!-- --> 343 <!-- The following properties are for internal use only. These should not be modified.--> 344 <!-- --> 345 <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/> 346 <property xil_pn:name="PROP_DesignName" xil_pn:value="waf_demo" xil_pn:valueState="non-default"/> 347 <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/> 348 <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> 349 <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/> 350 <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/> 351 <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> 352 <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> 353 <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> 354 <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2011-10-11T13:05:14" xil_pn:valueState="non-default"/> 355 <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> 356 <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> 357 <property xil_pn:name="PROP_mapSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/> 358 <property xil_pn:name="PROP_parSmartGuideFileName" xil_pn:value="" xil_pn:valueState="non-default"/> 359 </properties> 360 361 <bindings/> 362 363 <autoManagedFiles> 364 <!-- The following files are identified by `include statements in verilog --> 365 <!-- source files and are automatically managed by Project Navigator. --> 366 <!-- --> 367 <!-- Do not hand-edit this section, as it will be overwritten when the --> 368 <!-- project is analyzed based on files automatically identified as --> 369 <!-- include files. --> 370 </autoManagedFiles> 371 372 </project>