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1127 lines
30 KiB
C
1127 lines
30 KiB
C
/*
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* M68K helper routines
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*
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* Copyright (c) 2007 CodeSourcery
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "exec/exec-all.h"
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#include "exec/cpu_ldst.h"
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#include "semihosting/semihost.h"
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#if !defined(CONFIG_USER_ONLY)
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static void cf_rte(CPUM68KState *env)
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{
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uint32_t sp;
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uint32_t fmt;
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sp = env->aregs[7];
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fmt = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
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env->pc = cpu_ldl_mmuidx_ra(env, sp + 4, MMU_KERNEL_IDX, 0);
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sp |= (fmt >> 28) & 3;
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env->aregs[7] = sp + 8;
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cpu_m68k_set_sr(env, fmt);
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}
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static void m68k_rte(CPUM68KState *env)
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{
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uint32_t sp;
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uint16_t fmt;
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uint16_t sr;
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sp = env->aregs[7];
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throwaway:
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sr = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
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sp += 2;
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env->pc = cpu_ldl_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
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sp += 4;
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if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
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/* all except 68000 */
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fmt = cpu_lduw_mmuidx_ra(env, sp, MMU_KERNEL_IDX, 0);
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sp += 2;
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switch (fmt >> 12) {
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case 0:
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break;
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case 1:
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env->aregs[7] = sp;
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cpu_m68k_set_sr(env, sr);
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goto throwaway;
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case 2:
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case 3:
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sp += 4;
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break;
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case 4:
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sp += 8;
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break;
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case 7:
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sp += 52;
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break;
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}
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}
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env->aregs[7] = sp;
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cpu_m68k_set_sr(env, sr);
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}
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static const char *m68k_exception_name(int index)
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{
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switch (index) {
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case EXCP_ACCESS:
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return "Access Fault";
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case EXCP_ADDRESS:
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return "Address Error";
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case EXCP_ILLEGAL:
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return "Illegal Instruction";
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case EXCP_DIV0:
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return "Divide by Zero";
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case EXCP_CHK:
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return "CHK/CHK2";
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case EXCP_TRAPCC:
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return "FTRAPcc, TRAPcc, TRAPV";
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case EXCP_PRIVILEGE:
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return "Privilege Violation";
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case EXCP_TRACE:
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return "Trace";
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case EXCP_LINEA:
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return "A-Line";
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case EXCP_LINEF:
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return "F-Line";
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case EXCP_DEBEGBP: /* 68020/030 only */
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return "Copro Protocol Violation";
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case EXCP_FORMAT:
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return "Format Error";
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case EXCP_UNINITIALIZED:
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return "Uninitialized Interrupt";
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case EXCP_SPURIOUS:
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return "Spurious Interrupt";
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case EXCP_INT_LEVEL_1:
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return "Level 1 Interrupt";
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case EXCP_INT_LEVEL_1 + 1:
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return "Level 2 Interrupt";
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case EXCP_INT_LEVEL_1 + 2:
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return "Level 3 Interrupt";
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case EXCP_INT_LEVEL_1 + 3:
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return "Level 4 Interrupt";
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case EXCP_INT_LEVEL_1 + 4:
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return "Level 5 Interrupt";
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case EXCP_INT_LEVEL_1 + 5:
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return "Level 6 Interrupt";
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case EXCP_INT_LEVEL_1 + 6:
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return "Level 7 Interrupt";
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case EXCP_TRAP0:
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return "TRAP #0";
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case EXCP_TRAP0 + 1:
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return "TRAP #1";
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case EXCP_TRAP0 + 2:
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return "TRAP #2";
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case EXCP_TRAP0 + 3:
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return "TRAP #3";
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case EXCP_TRAP0 + 4:
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return "TRAP #4";
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case EXCP_TRAP0 + 5:
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return "TRAP #5";
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case EXCP_TRAP0 + 6:
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return "TRAP #6";
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case EXCP_TRAP0 + 7:
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return "TRAP #7";
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case EXCP_TRAP0 + 8:
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return "TRAP #8";
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case EXCP_TRAP0 + 9:
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return "TRAP #9";
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case EXCP_TRAP0 + 10:
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return "TRAP #10";
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case EXCP_TRAP0 + 11:
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return "TRAP #11";
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case EXCP_TRAP0 + 12:
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return "TRAP #12";
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case EXCP_TRAP0 + 13:
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return "TRAP #13";
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case EXCP_TRAP0 + 14:
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return "TRAP #14";
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case EXCP_TRAP0 + 15:
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return "TRAP #15";
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case EXCP_FP_BSUN:
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return "FP Branch/Set on unordered condition";
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case EXCP_FP_INEX:
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return "FP Inexact Result";
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case EXCP_FP_DZ:
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return "FP Divide by Zero";
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case EXCP_FP_UNFL:
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return "FP Underflow";
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case EXCP_FP_OPERR:
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return "FP Operand Error";
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case EXCP_FP_OVFL:
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return "FP Overflow";
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case EXCP_FP_SNAN:
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return "FP Signaling NAN";
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case EXCP_FP_UNIMP:
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return "FP Unimplemented Data Type";
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case EXCP_MMU_CONF: /* 68030/68851 only */
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return "MMU Configuration Error";
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case EXCP_MMU_ILLEGAL: /* 68851 only */
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return "MMU Illegal Operation";
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case EXCP_MMU_ACCESS: /* 68851 only */
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return "MMU Access Level Violation";
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case 64 ... 255:
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return "User Defined Vector";
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}
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return "Unassigned";
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}
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static void cf_interrupt_all(CPUM68KState *env, int is_hw)
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{
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CPUState *cs = env_cpu(env);
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uint32_t sp;
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uint32_t sr;
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uint32_t fmt;
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uint32_t retaddr;
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uint32_t vector;
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fmt = 0;
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retaddr = env->pc;
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if (!is_hw) {
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switch (cs->exception_index) {
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case EXCP_RTE:
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/* Return from an exception. */
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cf_rte(env);
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return;
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case EXCP_HALT_INSN:
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if (semihosting_enabled((env->sr & SR_S) == 0)
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&& (env->pc & 3) == 0
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&& cpu_lduw_code(env, env->pc - 4) == 0x4e71
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&& cpu_ldl_code(env, env->pc) == 0x4e7bf000) {
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env->pc += 4;
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do_m68k_semihosting(env, env->dregs[0]);
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return;
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}
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cs->halted = 1;
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cs->exception_index = EXCP_HLT;
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cpu_loop_exit(cs);
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return;
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}
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}
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vector = cs->exception_index << 2;
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sr = env->sr | cpu_m68k_get_ccr(env);
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
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++count, m68k_exception_name(cs->exception_index),
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vector, env->pc, env->aregs[7], sr);
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}
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fmt |= 0x40000000;
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fmt |= vector << 16;
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fmt |= sr;
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env->sr |= SR_S;
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if (is_hw) {
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env->sr = (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
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env->sr &= ~SR_M;
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}
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m68k_switch_sp(env);
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sp = env->aregs[7];
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fmt |= (sp & 3) << 28;
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/* ??? This could cause MMU faults. */
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sp &= ~3;
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, retaddr, MMU_KERNEL_IDX, 0);
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, fmt, MMU_KERNEL_IDX, 0);
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env->aregs[7] = sp;
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/* Jump to vector. */
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env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
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}
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static inline void do_stack_frame(CPUM68KState *env, uint32_t *sp,
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uint16_t format, uint16_t sr,
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uint32_t addr, uint32_t retaddr)
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{
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if (m68k_feature(env, M68K_FEATURE_QUAD_MULDIV)) {
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/* all except 68000 */
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CPUState *cs = env_cpu(env);
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switch (format) {
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case 4:
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*sp -= 4;
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cpu_stl_mmuidx_ra(env, *sp, env->pc, MMU_KERNEL_IDX, 0);
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*sp -= 4;
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cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
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break;
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case 3:
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case 2:
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*sp -= 4;
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cpu_stl_mmuidx_ra(env, *sp, addr, MMU_KERNEL_IDX, 0);
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break;
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}
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*sp -= 2;
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cpu_stw_mmuidx_ra(env, *sp, (format << 12) + (cs->exception_index << 2),
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MMU_KERNEL_IDX, 0);
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}
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*sp -= 4;
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cpu_stl_mmuidx_ra(env, *sp, retaddr, MMU_KERNEL_IDX, 0);
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*sp -= 2;
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cpu_stw_mmuidx_ra(env, *sp, sr, MMU_KERNEL_IDX, 0);
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}
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static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
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{
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CPUState *cs = env_cpu(env);
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uint32_t sp;
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uint32_t vector;
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uint16_t sr, oldsr;
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if (!is_hw) {
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switch (cs->exception_index) {
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case EXCP_RTE:
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/* Return from an exception. */
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m68k_rte(env);
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return;
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}
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}
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vector = cs->exception_index << 2;
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sr = env->sr | cpu_m68k_get_ccr(env);
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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static int count;
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qemu_log("INT %6d: %s(%#x) pc=%08x sp=%08x sr=%04x\n",
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++count, m68k_exception_name(cs->exception_index),
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vector, env->pc, env->aregs[7], sr);
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}
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/*
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* MC68040UM/AD, chapter 9.3.10
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*/
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/* "the processor first make an internal copy" */
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oldsr = sr;
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/* "set the mode to supervisor" */
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sr |= SR_S;
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/* "suppress tracing" */
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sr &= ~SR_T;
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/* "sets the processor interrupt mask" */
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if (is_hw) {
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sr |= (env->sr & ~SR_I) | (env->pending_level << SR_I_SHIFT);
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}
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cpu_m68k_set_sr(env, sr);
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sp = env->aregs[7];
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if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
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sp &= ~1;
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}
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switch (cs->exception_index) {
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case EXCP_ACCESS:
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if (env->mmu.fault) {
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cpu_abort(cs, "DOUBLE MMU FAULT\n");
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}
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env->mmu.fault = true;
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/* push data 3 */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* push data 2 */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* push data 1 */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 1 / push data 0 */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 1 address */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 2 data */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 2 address */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 3 data */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 3 address */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
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/* fault address */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
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/* write back 1 status */
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sp -= 2;
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cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 2 status */
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sp -= 2;
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cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* write back 3 status */
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sp -= 2;
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cpu_stw_mmuidx_ra(env, sp, 0, MMU_KERNEL_IDX, 0);
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/* special status word */
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sp -= 2;
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cpu_stw_mmuidx_ra(env, sp, env->mmu.ssw, MMU_KERNEL_IDX, 0);
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/* effective address */
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sp -= 4;
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cpu_stl_mmuidx_ra(env, sp, env->mmu.ar, MMU_KERNEL_IDX, 0);
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do_stack_frame(env, &sp, 7, oldsr, 0, env->pc);
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env->mmu.fault = false;
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if (qemu_loglevel_mask(CPU_LOG_INT)) {
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qemu_log(" "
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"ssw: %08x ea: %08x sfc: %d dfc: %d\n",
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env->mmu.ssw, env->mmu.ar, env->sfc, env->dfc);
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}
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break;
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case EXCP_ILLEGAL:
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do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
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break;
|
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|
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case EXCP_ADDRESS:
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do_stack_frame(env, &sp, 2, oldsr, 0, env->pc);
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break;
|
|
|
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case EXCP_CHK:
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case EXCP_DIV0:
|
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case EXCP_TRACE:
|
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case EXCP_TRAPCC:
|
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do_stack_frame(env, &sp, 2, oldsr, env->mmu.ar, env->pc);
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break;
|
|
|
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case EXCP_SPURIOUS ... EXCP_INT_LEVEL_7:
|
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if (is_hw && (oldsr & SR_M)) {
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do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
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oldsr = sr;
|
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env->aregs[7] = sp;
|
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cpu_m68k_set_sr(env, sr & ~SR_M);
|
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sp = env->aregs[7];
|
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if (!m68k_feature(env, M68K_FEATURE_UNALIGNED_DATA)) {
|
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sp &= ~1;
|
|
}
|
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do_stack_frame(env, &sp, 1, oldsr, 0, env->pc);
|
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break;
|
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}
|
|
/* fall through */
|
|
|
|
default:
|
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do_stack_frame(env, &sp, 0, oldsr, 0, env->pc);
|
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break;
|
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}
|
|
|
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env->aregs[7] = sp;
|
|
/* Jump to vector. */
|
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env->pc = cpu_ldl_mmuidx_ra(env, env->vbr + vector, MMU_KERNEL_IDX, 0);
|
|
}
|
|
|
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static void do_interrupt_all(CPUM68KState *env, int is_hw)
|
|
{
|
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if (m68k_feature(env, M68K_FEATURE_M68K)) {
|
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m68k_interrupt_all(env, is_hw);
|
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return;
|
|
}
|
|
cf_interrupt_all(env, is_hw);
|
|
}
|
|
|
|
void m68k_cpu_do_interrupt(CPUState *cs)
|
|
{
|
|
M68kCPU *cpu = M68K_CPU(cs);
|
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CPUM68KState *env = &cpu->env;
|
|
|
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do_interrupt_all(env, 0);
|
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}
|
|
|
|
static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
|
|
{
|
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do_interrupt_all(env, 1);
|
|
}
|
|
|
|
void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
|
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unsigned size, MMUAccessType access_type,
|
|
int mmu_idx, MemTxAttrs attrs,
|
|
MemTxResult response, uintptr_t retaddr)
|
|
{
|
|
M68kCPU *cpu = M68K_CPU(cs);
|
|
CPUM68KState *env = &cpu->env;
|
|
|
|
cpu_restore_state(cs, retaddr);
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|
|
|
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
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env->mmu.mmusr = 0;
|
|
|
|
/*
|
|
* According to the MC68040 users manual the ATC bit of the SSW is
|
|
* used to distinguish between ATC faults and physical bus errors.
|
|
* In the case of a bus error e.g. during nubus read from an empty
|
|
* slot this bit should not be set
|
|
*/
|
|
if (response != MEMTX_DECODE_ERROR) {
|
|
env->mmu.ssw |= M68K_ATC_040;
|
|
}
|
|
|
|
/* FIXME: manage MMU table access error */
|
|
env->mmu.ssw &= ~M68K_TM_040;
|
|
if (env->sr & SR_S) { /* SUPERVISOR */
|
|
env->mmu.ssw |= M68K_TM_040_SUPER;
|
|
}
|
|
if (access_type == MMU_INST_FETCH) { /* instruction or data */
|
|
env->mmu.ssw |= M68K_TM_040_CODE;
|
|
} else {
|
|
env->mmu.ssw |= M68K_TM_040_DATA;
|
|
}
|
|
env->mmu.ssw &= ~M68K_BA_SIZE_MASK;
|
|
switch (size) {
|
|
case 1:
|
|
env->mmu.ssw |= M68K_BA_SIZE_BYTE;
|
|
break;
|
|
case 2:
|
|
env->mmu.ssw |= M68K_BA_SIZE_WORD;
|
|
break;
|
|
case 4:
|
|
env->mmu.ssw |= M68K_BA_SIZE_LONG;
|
|
break;
|
|
}
|
|
|
|
if (access_type != MMU_DATA_STORE) {
|
|
env->mmu.ssw |= M68K_RW_040;
|
|
}
|
|
|
|
env->mmu.ar = addr;
|
|
|
|
cs->exception_index = EXCP_ACCESS;
|
|
cpu_loop_exit(cs);
|
|
}
|
|
}
|
|
|
|
bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
|
{
|
|
M68kCPU *cpu = M68K_CPU(cs);
|
|
CPUM68KState *env = &cpu->env;
|
|
|
|
if (interrupt_request & CPU_INTERRUPT_HARD
|
|
&& ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) {
|
|
/*
|
|
* Real hardware gets the interrupt vector via an IACK cycle
|
|
* at this point. Current emulated hardware doesn't rely on
|
|
* this, so we provide/save the vector when the interrupt is
|
|
* first signalled.
|
|
*/
|
|
cs->exception_index = env->pending_vector;
|
|
do_interrupt_m68k_hardirq(env);
|
|
return true;
|
|
}
|
|
return false;
|
|
}
|
|
|
|
#endif /* !CONFIG_USER_ONLY */
|
|
|
|
G_NORETURN static void
|
|
raise_exception_ra(CPUM68KState *env, int tt, uintptr_t raddr)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
cs->exception_index = tt;
|
|
cpu_loop_exit_restore(cs, raddr);
|
|
}
|
|
|
|
G_NORETURN static void raise_exception(CPUM68KState *env, int tt)
|
|
{
|
|
raise_exception_ra(env, tt, 0);
|
|
}
|
|
|
|
void HELPER(raise_exception)(CPUM68KState *env, uint32_t tt)
|
|
{
|
|
raise_exception(env, tt);
|
|
}
|
|
|
|
G_NORETURN static void
|
|
raise_exception_format2(CPUM68KState *env, int tt, int ilen, uintptr_t raddr)
|
|
{
|
|
CPUState *cs = env_cpu(env);
|
|
|
|
cs->exception_index = tt;
|
|
|
|
/* Recover PC and CC_OP for the beginning of the insn. */
|
|
cpu_restore_state(cs, raddr);
|
|
|
|
/* Flags are current in env->cc_*, or are undefined. */
|
|
env->cc_op = CC_OP_FLAGS;
|
|
|
|
/*
|
|
* Remember original pc in mmu.ar, for the Format 2 stack frame.
|
|
* Adjust PC to end of the insn.
|
|
*/
|
|
env->mmu.ar = env->pc;
|
|
env->pc += ilen;
|
|
|
|
cpu_loop_exit(cs);
|
|
}
|
|
|
|
void HELPER(divuw)(CPUM68KState *env, int destr, uint32_t den, int ilen)
|
|
{
|
|
uint32_t num = env->dregs[destr];
|
|
uint32_t quot, rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
if (quot > 0xffff) {
|
|
env->cc_v = -1;
|
|
/*
|
|
* real 68040 keeps N and unset Z on overflow,
|
|
* whereas documentation says "undefined"
|
|
*/
|
|
env->cc_z = 1;
|
|
return;
|
|
}
|
|
env->dregs[destr] = deposit32(quot, 16, 16, rem);
|
|
env->cc_z = (int16_t)quot;
|
|
env->cc_n = (int16_t)quot;
|
|
env->cc_v = 0;
|
|
}
|
|
|
|
void HELPER(divsw)(CPUM68KState *env, int destr, int32_t den, int ilen)
|
|
{
|
|
int32_t num = env->dregs[destr];
|
|
uint32_t quot, rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if overflow/div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
if (quot != (int16_t)quot) {
|
|
env->cc_v = -1;
|
|
/* nothing else is modified */
|
|
/*
|
|
* real 68040 keeps N and unset Z on overflow,
|
|
* whereas documentation says "undefined"
|
|
*/
|
|
env->cc_z = 1;
|
|
return;
|
|
}
|
|
env->dregs[destr] = deposit32(quot, 16, 16, rem);
|
|
env->cc_z = (int16_t)quot;
|
|
env->cc_n = (int16_t)quot;
|
|
env->cc_v = 0;
|
|
}
|
|
|
|
void HELPER(divul)(CPUM68KState *env, int numr, int regr,
|
|
uint32_t den, int ilen)
|
|
{
|
|
uint32_t num = env->dregs[numr];
|
|
uint32_t quot, rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
env->cc_z = quot;
|
|
env->cc_n = quot;
|
|
env->cc_v = 0;
|
|
|
|
if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
|
|
if (numr == regr) {
|
|
env->dregs[numr] = quot;
|
|
} else {
|
|
env->dregs[regr] = rem;
|
|
}
|
|
} else {
|
|
env->dregs[regr] = rem;
|
|
env->dregs[numr] = quot;
|
|
}
|
|
}
|
|
|
|
void HELPER(divsl)(CPUM68KState *env, int numr, int regr,
|
|
int32_t den, int ilen)
|
|
{
|
|
int32_t num = env->dregs[numr];
|
|
int32_t quot, rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if overflow/div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
env->cc_z = quot;
|
|
env->cc_n = quot;
|
|
env->cc_v = 0;
|
|
|
|
if (m68k_feature(env, M68K_FEATURE_CF_ISA_A)) {
|
|
if (numr == regr) {
|
|
env->dregs[numr] = quot;
|
|
} else {
|
|
env->dregs[regr] = rem;
|
|
}
|
|
} else {
|
|
env->dregs[regr] = rem;
|
|
env->dregs[numr] = quot;
|
|
}
|
|
}
|
|
|
|
void HELPER(divull)(CPUM68KState *env, int numr, int regr,
|
|
uint32_t den, int ilen)
|
|
{
|
|
uint64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
|
|
uint64_t quot;
|
|
uint32_t rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if overflow/div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
if (quot > 0xffffffffULL) {
|
|
env->cc_v = -1;
|
|
/*
|
|
* real 68040 keeps N and unset Z on overflow,
|
|
* whereas documentation says "undefined"
|
|
*/
|
|
env->cc_z = 1;
|
|
return;
|
|
}
|
|
env->cc_z = quot;
|
|
env->cc_n = quot;
|
|
env->cc_v = 0;
|
|
|
|
/*
|
|
* If Dq and Dr are the same, the quotient is returned.
|
|
* therefore we set Dq last.
|
|
*/
|
|
|
|
env->dregs[regr] = rem;
|
|
env->dregs[numr] = quot;
|
|
}
|
|
|
|
void HELPER(divsll)(CPUM68KState *env, int numr, int regr,
|
|
int32_t den, int ilen)
|
|
{
|
|
int64_t num = deposit64(env->dregs[numr], 32, 32, env->dregs[regr]);
|
|
int64_t quot;
|
|
int32_t rem;
|
|
|
|
env->cc_c = 0; /* always cleared, even if overflow/div0 */
|
|
|
|
if (den == 0) {
|
|
raise_exception_format2(env, EXCP_DIV0, ilen, GETPC());
|
|
}
|
|
quot = num / den;
|
|
rem = num % den;
|
|
|
|
if (quot != (int32_t)quot) {
|
|
env->cc_v = -1;
|
|
/*
|
|
* real 68040 keeps N and unset Z on overflow,
|
|
* whereas documentation says "undefined"
|
|
*/
|
|
env->cc_z = 1;
|
|
return;
|
|
}
|
|
env->cc_z = quot;
|
|
env->cc_n = quot;
|
|
env->cc_v = 0;
|
|
|
|
/*
|
|
* If Dq and Dr are the same, the quotient is returned.
|
|
* therefore we set Dq last.
|
|
*/
|
|
|
|
env->dregs[regr] = rem;
|
|
env->dregs[numr] = quot;
|
|
}
|
|
|
|
/* We're executing in a serial context -- no need to be atomic. */
|
|
void HELPER(cas2w)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
|
|
{
|
|
uint32_t Dc1 = extract32(regs, 9, 3);
|
|
uint32_t Dc2 = extract32(regs, 6, 3);
|
|
uint32_t Du1 = extract32(regs, 3, 3);
|
|
uint32_t Du2 = extract32(regs, 0, 3);
|
|
int16_t c1 = env->dregs[Dc1];
|
|
int16_t c2 = env->dregs[Dc2];
|
|
int16_t u1 = env->dregs[Du1];
|
|
int16_t u2 = env->dregs[Du2];
|
|
int16_t l1, l2;
|
|
uintptr_t ra = GETPC();
|
|
|
|
l1 = cpu_lduw_data_ra(env, a1, ra);
|
|
l2 = cpu_lduw_data_ra(env, a2, ra);
|
|
if (l1 == c1 && l2 == c2) {
|
|
cpu_stw_data_ra(env, a1, u1, ra);
|
|
cpu_stw_data_ra(env, a2, u2, ra);
|
|
}
|
|
|
|
if (c1 != l1) {
|
|
env->cc_n = l1;
|
|
env->cc_v = c1;
|
|
} else {
|
|
env->cc_n = l2;
|
|
env->cc_v = c2;
|
|
}
|
|
env->cc_op = CC_OP_CMPW;
|
|
env->dregs[Dc1] = deposit32(env->dregs[Dc1], 0, 16, l1);
|
|
env->dregs[Dc2] = deposit32(env->dregs[Dc2], 0, 16, l2);
|
|
}
|
|
|
|
static void do_cas2l(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2,
|
|
bool parallel)
|
|
{
|
|
uint32_t Dc1 = extract32(regs, 9, 3);
|
|
uint32_t Dc2 = extract32(regs, 6, 3);
|
|
uint32_t Du1 = extract32(regs, 3, 3);
|
|
uint32_t Du2 = extract32(regs, 0, 3);
|
|
uint32_t c1 = env->dregs[Dc1];
|
|
uint32_t c2 = env->dregs[Dc2];
|
|
uint32_t u1 = env->dregs[Du1];
|
|
uint32_t u2 = env->dregs[Du2];
|
|
uint32_t l1, l2;
|
|
uintptr_t ra = GETPC();
|
|
#if defined(CONFIG_ATOMIC64)
|
|
int mmu_idx = cpu_mmu_index(env, 0);
|
|
MemOpIdx oi = make_memop_idx(MO_BEUQ, mmu_idx);
|
|
#endif
|
|
|
|
if (parallel) {
|
|
/* We're executing in a parallel context -- must be atomic. */
|
|
#ifdef CONFIG_ATOMIC64
|
|
uint64_t c, u, l;
|
|
if ((a1 & 7) == 0 && a2 == a1 + 4) {
|
|
c = deposit64(c2, 32, 32, c1);
|
|
u = deposit64(u2, 32, 32, u1);
|
|
l = cpu_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra);
|
|
l1 = l >> 32;
|
|
l2 = l;
|
|
} else if ((a2 & 7) == 0 && a1 == a2 + 4) {
|
|
c = deposit64(c1, 32, 32, c2);
|
|
u = deposit64(u1, 32, 32, u2);
|
|
l = cpu_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra);
|
|
l2 = l >> 32;
|
|
l1 = l;
|
|
} else
|
|
#endif
|
|
{
|
|
/* Tell the main loop we need to serialize this insn. */
|
|
cpu_loop_exit_atomic(env_cpu(env), ra);
|
|
}
|
|
} else {
|
|
/* We're executing in a serial context -- no need to be atomic. */
|
|
l1 = cpu_ldl_data_ra(env, a1, ra);
|
|
l2 = cpu_ldl_data_ra(env, a2, ra);
|
|
if (l1 == c1 && l2 == c2) {
|
|
cpu_stl_data_ra(env, a1, u1, ra);
|
|
cpu_stl_data_ra(env, a2, u2, ra);
|
|
}
|
|
}
|
|
|
|
if (c1 != l1) {
|
|
env->cc_n = l1;
|
|
env->cc_v = c1;
|
|
} else {
|
|
env->cc_n = l2;
|
|
env->cc_v = c2;
|
|
}
|
|
env->cc_op = CC_OP_CMPL;
|
|
env->dregs[Dc1] = l1;
|
|
env->dregs[Dc2] = l2;
|
|
}
|
|
|
|
void HELPER(cas2l)(CPUM68KState *env, uint32_t regs, uint32_t a1, uint32_t a2)
|
|
{
|
|
do_cas2l(env, regs, a1, a2, false);
|
|
}
|
|
|
|
void HELPER(cas2l_parallel)(CPUM68KState *env, uint32_t regs, uint32_t a1,
|
|
uint32_t a2)
|
|
{
|
|
do_cas2l(env, regs, a1, a2, true);
|
|
}
|
|
|
|
struct bf_data {
|
|
uint32_t addr;
|
|
uint32_t bofs;
|
|
uint32_t blen;
|
|
uint32_t len;
|
|
};
|
|
|
|
static struct bf_data bf_prep(uint32_t addr, int32_t ofs, uint32_t len)
|
|
{
|
|
int bofs, blen;
|
|
|
|
/* Bound length; map 0 to 32. */
|
|
len = ((len - 1) & 31) + 1;
|
|
|
|
/* Note that ofs is signed. */
|
|
addr += ofs / 8;
|
|
bofs = ofs % 8;
|
|
if (bofs < 0) {
|
|
bofs += 8;
|
|
addr -= 1;
|
|
}
|
|
|
|
/*
|
|
* Compute the number of bytes required (minus one) to
|
|
* satisfy the bitfield.
|
|
*/
|
|
blen = (bofs + len - 1) / 8;
|
|
|
|
/*
|
|
* Canonicalize the bit offset for data loaded into a 64-bit big-endian
|
|
* word. For the cases where BLEN is not a power of 2, adjust ADDR so
|
|
* that we can use the next power of two sized load without crossing a
|
|
* page boundary, unless the field itself crosses the boundary.
|
|
*/
|
|
switch (blen) {
|
|
case 0:
|
|
bofs += 56;
|
|
break;
|
|
case 1:
|
|
bofs += 48;
|
|
break;
|
|
case 2:
|
|
if (addr & 1) {
|
|
bofs += 8;
|
|
addr -= 1;
|
|
}
|
|
/* fallthru */
|
|
case 3:
|
|
bofs += 32;
|
|
break;
|
|
case 4:
|
|
if (addr & 3) {
|
|
bofs += 8 * (addr & 3);
|
|
addr &= -4;
|
|
}
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
return (struct bf_data){
|
|
.addr = addr,
|
|
.bofs = bofs,
|
|
.blen = blen,
|
|
.len = len,
|
|
};
|
|
}
|
|
|
|
static uint64_t bf_load(CPUM68KState *env, uint32_t addr, int blen,
|
|
uintptr_t ra)
|
|
{
|
|
switch (blen) {
|
|
case 0:
|
|
return cpu_ldub_data_ra(env, addr, ra);
|
|
case 1:
|
|
return cpu_lduw_data_ra(env, addr, ra);
|
|
case 2:
|
|
case 3:
|
|
return cpu_ldl_data_ra(env, addr, ra);
|
|
case 4:
|
|
return cpu_ldq_data_ra(env, addr, ra);
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
static void bf_store(CPUM68KState *env, uint32_t addr, int blen,
|
|
uint64_t data, uintptr_t ra)
|
|
{
|
|
switch (blen) {
|
|
case 0:
|
|
cpu_stb_data_ra(env, addr, data, ra);
|
|
break;
|
|
case 1:
|
|
cpu_stw_data_ra(env, addr, data, ra);
|
|
break;
|
|
case 2:
|
|
case 3:
|
|
cpu_stl_data_ra(env, addr, data, ra);
|
|
break;
|
|
case 4:
|
|
cpu_stq_data_ra(env, addr, data, ra);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
}
|
|
|
|
uint32_t HELPER(bfexts_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
|
|
return (int64_t)(data << d.bofs) >> (64 - d.len);
|
|
}
|
|
|
|
uint64_t HELPER(bfextu_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
|
|
/*
|
|
* Put CC_N at the top of the high word; put the zero-extended value
|
|
* at the bottom of the low word.
|
|
*/
|
|
data <<= d.bofs;
|
|
data >>= 64 - d.len;
|
|
data |= data << (64 - d.len);
|
|
|
|
return data;
|
|
}
|
|
|
|
uint32_t HELPER(bfins_mem)(CPUM68KState *env, uint32_t addr, uint32_t val,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
|
|
|
|
data = (data & ~mask) | (((uint64_t)val << (64 - d.len)) >> d.bofs);
|
|
|
|
bf_store(env, d.addr, d.blen, data, ra);
|
|
|
|
/* The field at the top of the word is also CC_N for CC_OP_LOGIC. */
|
|
return val << (32 - d.len);
|
|
}
|
|
|
|
uint32_t HELPER(bfchg_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
|
|
|
|
bf_store(env, d.addr, d.blen, data ^ mask, ra);
|
|
|
|
return ((data & mask) << d.bofs) >> 32;
|
|
}
|
|
|
|
uint32_t HELPER(bfclr_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
|
|
|
|
bf_store(env, d.addr, d.blen, data & ~mask, ra);
|
|
|
|
return ((data & mask) << d.bofs) >> 32;
|
|
}
|
|
|
|
uint32_t HELPER(bfset_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
|
|
|
|
bf_store(env, d.addr, d.blen, data | mask, ra);
|
|
|
|
return ((data & mask) << d.bofs) >> 32;
|
|
}
|
|
|
|
uint32_t HELPER(bfffo_reg)(uint32_t n, uint32_t ofs, uint32_t len)
|
|
{
|
|
return (n ? clz32(n) : len) + ofs;
|
|
}
|
|
|
|
uint64_t HELPER(bfffo_mem)(CPUM68KState *env, uint32_t addr,
|
|
int32_t ofs, uint32_t len)
|
|
{
|
|
uintptr_t ra = GETPC();
|
|
struct bf_data d = bf_prep(addr, ofs, len);
|
|
uint64_t data = bf_load(env, d.addr, d.blen, ra);
|
|
uint64_t mask = -1ull << (64 - d.len) >> d.bofs;
|
|
uint64_t n = (data & mask) << d.bofs;
|
|
uint32_t ffo = helper_bfffo_reg(n >> 32, ofs, d.len);
|
|
|
|
/*
|
|
* Return FFO in the low word and N in the high word.
|
|
* Note that because of MASK and the shift, the low word
|
|
* is already zero.
|
|
*/
|
|
return n | ffo;
|
|
}
|
|
|
|
void HELPER(chk)(CPUM68KState *env, int32_t val, int32_t ub)
|
|
{
|
|
/*
|
|
* From the specs:
|
|
* X: Not affected, C,V,Z: Undefined,
|
|
* N: Set if val < 0; cleared if val > ub, undefined otherwise
|
|
* We implement here values found from a real MC68040:
|
|
* X,V,Z: Not affected
|
|
* N: Set if val < 0; cleared if val >= 0
|
|
* C: if 0 <= ub: set if val < 0 or val > ub, cleared otherwise
|
|
* if 0 > ub: set if val > ub and val < 0, cleared otherwise
|
|
*/
|
|
env->cc_n = val;
|
|
env->cc_c = 0 <= ub ? val < 0 || val > ub : val > ub && val < 0;
|
|
|
|
if (val < 0 || val > ub) {
|
|
raise_exception_format2(env, EXCP_CHK, 2, GETPC());
|
|
}
|
|
}
|
|
|
|
void HELPER(chk2)(CPUM68KState *env, int32_t val, int32_t lb, int32_t ub)
|
|
{
|
|
/*
|
|
* From the specs:
|
|
* X: Not affected, N,V: Undefined,
|
|
* Z: Set if val is equal to lb or ub
|
|
* C: Set if val < lb or val > ub, cleared otherwise
|
|
* We implement here values found from a real MC68040:
|
|
* X,N,V: Not affected
|
|
* Z: Set if val is equal to lb or ub
|
|
* C: if lb <= ub: set if val < lb or val > ub, cleared otherwise
|
|
* if lb > ub: set if val > ub and val < lb, cleared otherwise
|
|
*/
|
|
env->cc_z = val != lb && val != ub;
|
|
env->cc_c = lb <= ub ? val < lb || val > ub : val > ub && val < lb;
|
|
|
|
if (env->cc_c) {
|
|
raise_exception_format2(env, EXCP_CHK, 4, GETPC());
|
|
}
|
|
}
|