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775 lines
25 KiB
C
775 lines
25 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* QEMU LoongArch CPU
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*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/qemu-print.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "sysemu/qtest.h"
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#include "exec/exec-all.h"
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#include "qapi/qapi-commands-machine-target.h"
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#include "cpu.h"
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#include "internals.h"
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#include "fpu/softfloat-helpers.h"
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#include "cpu-csr.h"
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#include "sysemu/reset.h"
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const char * const regnames[32] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
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"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
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};
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const char * const fregnames[32] = {
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"f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
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"f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
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"f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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};
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static const char * const excp_names[] = {
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[EXCCODE_INT] = "Interrupt",
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[EXCCODE_PIL] = "Page invalid exception for load",
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[EXCCODE_PIS] = "Page invalid exception for store",
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[EXCCODE_PIF] = "Page invalid exception for fetch",
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[EXCCODE_PME] = "Page modified exception",
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[EXCCODE_PNR] = "Page Not Readable exception",
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[EXCCODE_PNX] = "Page Not Executable exception",
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[EXCCODE_PPI] = "Page Privilege error",
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[EXCCODE_ADEF] = "Address error for instruction fetch",
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[EXCCODE_ADEM] = "Address error for Memory access",
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[EXCCODE_SYS] = "Syscall",
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[EXCCODE_BRK] = "Break",
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[EXCCODE_INE] = "Instruction Non-Existent",
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[EXCCODE_IPE] = "Instruction privilege error",
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[EXCCODE_FPD] = "Floating Point Disabled",
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[EXCCODE_FPE] = "Floating Point Exception",
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[EXCCODE_DBP] = "Debug breakpoint",
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[EXCCODE_BCE] = "Bound Check Exception",
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};
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const char *loongarch_exception_name(int32_t exception)
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{
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assert(excp_names[exception]);
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return excp_names[exception];
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}
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void G_NORETURN do_raise_exception(CPULoongArchState *env,
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uint32_t exception,
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uintptr_t pc)
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{
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CPUState *cs = env_cpu(env);
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qemu_log_mask(CPU_LOG_INT, "%s: %d (%s)\n",
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__func__,
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exception,
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loongarch_exception_name(exception));
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cs->exception_index = exception;
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cpu_loop_exit_restore(cs, pc);
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}
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static void loongarch_cpu_set_pc(CPUState *cs, vaddr value)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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env->pc = value;
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}
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static vaddr loongarch_cpu_get_pc(CPUState *cs)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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return env->pc;
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}
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#ifndef CONFIG_USER_ONLY
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#include "hw/loongarch/virt.h"
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void loongarch_cpu_set_irq(void *opaque, int irq, int level)
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{
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LoongArchCPU *cpu = opaque;
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CPULoongArchState *env = &cpu->env;
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CPUState *cs = CPU(cpu);
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if (irq < 0 || irq >= N_IRQS) {
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return;
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}
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env->CSR_ESTAT = deposit64(env->CSR_ESTAT, irq, 1, level != 0);
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if (FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS)) {
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cpu_interrupt(cs, CPU_INTERRUPT_HARD);
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} else {
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cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD);
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}
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}
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static inline bool cpu_loongarch_hw_interrupts_enabled(CPULoongArchState *env)
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{
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bool ret = 0;
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ret = (FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE) &&
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!(FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)));
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return ret;
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}
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/* Check if there is pending and not masked out interrupt */
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static inline bool cpu_loongarch_hw_interrupts_pending(CPULoongArchState *env)
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{
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uint32_t pending;
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uint32_t status;
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bool r;
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pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
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status = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
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r = (pending & status) != 0;
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return r;
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}
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static void loongarch_cpu_do_interrupt(CPUState *cs)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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bool update_badinstr = 1;
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int cause = -1;
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const char *name;
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bool tlbfill = FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR);
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uint32_t vec_size = FIELD_EX64(env->CSR_ECFG, CSR_ECFG, VS);
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if (cs->exception_index != EXCCODE_INT) {
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if (cs->exception_index < 0 ||
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cs->exception_index >= ARRAY_SIZE(excp_names)) {
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name = "unknown";
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} else {
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name = excp_names[cs->exception_index];
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}
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qemu_log_mask(CPU_LOG_INT,
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"%s enter: pc " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" TLBRERA " TARGET_FMT_lx " %s exception\n", __func__,
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env->pc, env->CSR_ERA, env->CSR_TLBRERA, name);
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}
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switch (cs->exception_index) {
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case EXCCODE_DBP:
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DCL, 1);
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, ECODE, 0xC);
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goto set_DERA;
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set_DERA:
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env->CSR_DERA = env->pc;
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DST, 1);
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env->pc = env->CSR_EENTRY + 0x480;
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break;
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case EXCCODE_INT:
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if (FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
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env->CSR_DBG = FIELD_DP64(env->CSR_DBG, CSR_DBG, DEI, 1);
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goto set_DERA;
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}
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QEMU_FALLTHROUGH;
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case EXCCODE_PIF:
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case EXCCODE_ADEF:
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cause = cs->exception_index;
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update_badinstr = 0;
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break;
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case EXCCODE_SYS:
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case EXCCODE_BRK:
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case EXCCODE_INE:
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case EXCCODE_IPE:
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case EXCCODE_FPD:
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case EXCCODE_FPE:
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case EXCCODE_BCE:
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env->CSR_BADV = env->pc;
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QEMU_FALLTHROUGH;
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case EXCCODE_ADEM:
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case EXCCODE_PIL:
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case EXCCODE_PIS:
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case EXCCODE_PME:
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case EXCCODE_PNR:
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case EXCCODE_PNX:
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case EXCCODE_PPI:
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cause = cs->exception_index;
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break;
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default:
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qemu_log("Error: exception(%d) has not been supported\n",
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cs->exception_index);
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abort();
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}
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if (update_badinstr) {
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env->CSR_BADI = cpu_ldl_code(env, env->pc);
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}
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/* Save PLV and IE */
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if (tlbfill) {
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env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PPLV,
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FIELD_EX64(env->CSR_CRMD,
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CSR_CRMD, PLV));
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env->CSR_TLBRPRMD = FIELD_DP64(env->CSR_TLBRPRMD, CSR_TLBRPRMD, PIE,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
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/* set the DA mode */
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
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env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA,
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PC, (env->pc >> 2));
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} else {
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env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ECODE,
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EXCODE_MCODE(cause));
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env->CSR_ESTAT = FIELD_DP64(env->CSR_ESTAT, CSR_ESTAT, ESUBCODE,
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EXCODE_SUBCODE(cause));
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env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PPLV,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV));
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env->CSR_PRMD = FIELD_DP64(env->CSR_PRMD, CSR_PRMD, PIE,
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FIELD_EX64(env->CSR_CRMD, CSR_CRMD, IE));
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env->CSR_ERA = env->pc;
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}
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
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env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
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if (vec_size) {
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vec_size = (1 << vec_size) * 4;
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}
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if (cs->exception_index == EXCCODE_INT) {
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/* Interrupt */
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uint32_t vector = 0;
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uint32_t pending = FIELD_EX64(env->CSR_ESTAT, CSR_ESTAT, IS);
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pending &= FIELD_EX64(env->CSR_ECFG, CSR_ECFG, LIE);
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/* Find the highest-priority interrupt. */
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vector = 31 - clz32(pending);
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env->pc = env->CSR_EENTRY + (EXCCODE_EXTERNAL_INT + vector) * vec_size;
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qemu_log_mask(CPU_LOG_INT,
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"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" cause %d\n" " A " TARGET_FMT_lx " D "
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TARGET_FMT_lx " vector = %d ExC " TARGET_FMT_lx "ExS"
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TARGET_FMT_lx "\n",
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__func__, env->pc, env->CSR_ERA,
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cause, env->CSR_BADV, env->CSR_DERA, vector,
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env->CSR_ECFG, env->CSR_ESTAT);
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} else {
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if (tlbfill) {
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env->pc = env->CSR_TLBRENTRY;
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} else {
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env->pc = env->CSR_EENTRY;
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env->pc += EXCODE_MCODE(cause) * vec_size;
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}
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qemu_log_mask(CPU_LOG_INT,
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"%s: PC " TARGET_FMT_lx " ERA " TARGET_FMT_lx
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" cause %d%s\n, ESTAT " TARGET_FMT_lx
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" EXCFG " TARGET_FMT_lx " BADVA " TARGET_FMT_lx
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"BADI " TARGET_FMT_lx " SYS_NUM " TARGET_FMT_lu
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" cpu %d asid " TARGET_FMT_lx "\n", __func__, env->pc,
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tlbfill ? env->CSR_TLBRERA : env->CSR_ERA,
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cause, tlbfill ? "(refill)" : "", env->CSR_ESTAT,
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env->CSR_ECFG,
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tlbfill ? env->CSR_TLBRBADV : env->CSR_BADV,
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env->CSR_BADI, env->gpr[11], cs->cpu_index,
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env->CSR_ASID);
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}
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cs->exception_index = -1;
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}
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static void loongarch_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
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vaddr addr, unsigned size,
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MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response,
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uintptr_t retaddr)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (access_type == MMU_INST_FETCH) {
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do_raise_exception(env, EXCCODE_ADEF, retaddr);
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} else {
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do_raise_exception(env, EXCCODE_ADEM, retaddr);
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}
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}
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static bool loongarch_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
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{
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if (interrupt_request & CPU_INTERRUPT_HARD) {
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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if (cpu_loongarch_hw_interrupts_enabled(env) &&
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cpu_loongarch_hw_interrupts_pending(env)) {
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/* Raise it */
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cs->exception_index = EXCCODE_INT;
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loongarch_cpu_do_interrupt(cs);
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return true;
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}
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}
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return false;
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}
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#endif
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#ifdef CONFIG_TCG
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static void loongarch_cpu_synchronize_from_tb(CPUState *cs,
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const TranslationBlock *tb)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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env->pc = tb_pc(tb);
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}
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static void loongarch_restore_state_to_opc(CPUState *cs,
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const TranslationBlock *tb,
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const uint64_t *data)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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env->pc = data[0];
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}
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#endif /* CONFIG_TCG */
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static bool loongarch_cpu_has_work(CPUState *cs)
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{
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#ifdef CONFIG_USER_ONLY
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return true;
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#else
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LoongArchCPU *cpu = LOONGARCH_CPU(cs);
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CPULoongArchState *env = &cpu->env;
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bool has_work = false;
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if ((cs->interrupt_request & CPU_INTERRUPT_HARD) &&
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cpu_loongarch_hw_interrupts_pending(env)) {
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has_work = true;
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}
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return has_work;
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#endif
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}
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static void loongarch_la464_initfn(Object *obj)
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{
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LoongArchCPU *cpu = LOONGARCH_CPU(obj);
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CPULoongArchState *env = &cpu->env;
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int i;
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for (i = 0; i < 21; i++) {
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env->cpucfg[i] = 0x0;
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}
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cpu->dtb_compatible = "loongarch,Loongson-3A5000";
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env->cpucfg[0] = 0x14c010; /* PRID */
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uint32_t data = 0;
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data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
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data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
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data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
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data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
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data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
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data = FIELD_DP32(data, CPUCFG1, UAL, 1);
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data = FIELD_DP32(data, CPUCFG1, RI, 1);
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data = FIELD_DP32(data, CPUCFG1, EP, 1);
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data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
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data = FIELD_DP32(data, CPUCFG1, HP, 1);
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data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
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env->cpucfg[1] = data;
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data = 0;
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data = FIELD_DP32(data, CPUCFG2, FP, 1);
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data = FIELD_DP32(data, CPUCFG2, FP_SP, 1);
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data = FIELD_DP32(data, CPUCFG2, FP_DP, 1);
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data = FIELD_DP32(data, CPUCFG2, FP_VER, 1);
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data = FIELD_DP32(data, CPUCFG2, LLFTP, 1);
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data = FIELD_DP32(data, CPUCFG2, LLFTP_VER, 1);
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data = FIELD_DP32(data, CPUCFG2, LAM, 1);
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env->cpucfg[2] = data;
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env->cpucfg[4] = 100 * 1000 * 1000; /* Crystal frequency */
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data = 0;
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data = FIELD_DP32(data, CPUCFG5, CC_MUL, 1);
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data = FIELD_DP32(data, CPUCFG5, CC_DIV, 1);
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env->cpucfg[5] = data;
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data = 0;
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data = FIELD_DP32(data, CPUCFG16, L1_IUPRE, 1);
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data = FIELD_DP32(data, CPUCFG16, L1_DPRE, 1);
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data = FIELD_DP32(data, CPUCFG16, L2_IUPRE, 1);
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data = FIELD_DP32(data, CPUCFG16, L2_IUUNIFY, 1);
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data = FIELD_DP32(data, CPUCFG16, L2_IUPRIV, 1);
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data = FIELD_DP32(data, CPUCFG16, L3_IUPRE, 1);
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data = FIELD_DP32(data, CPUCFG16, L3_IUUNIFY, 1);
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data = FIELD_DP32(data, CPUCFG16, L3_IUINCL, 1);
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env->cpucfg[16] = data;
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data = 0;
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data = FIELD_DP32(data, CPUCFG17, L1IU_WAYS, 3);
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data = FIELD_DP32(data, CPUCFG17, L1IU_SETS, 8);
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data = FIELD_DP32(data, CPUCFG17, L1IU_SIZE, 6);
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env->cpucfg[17] = data;
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data = 0;
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data = FIELD_DP32(data, CPUCFG18, L1D_WAYS, 3);
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data = FIELD_DP32(data, CPUCFG18, L1D_SETS, 8);
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data = FIELD_DP32(data, CPUCFG18, L1D_SIZE, 6);
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env->cpucfg[18] = data;
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data = 0;
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data = FIELD_DP32(data, CPUCFG19, L2IU_WAYS, 15);
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data = FIELD_DP32(data, CPUCFG19, L2IU_SETS, 8);
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data = FIELD_DP32(data, CPUCFG19, L2IU_SIZE, 6);
|
|
env->cpucfg[19] = data;
|
|
|
|
data = 0;
|
|
data = FIELD_DP32(data, CPUCFG20, L3IU_WAYS, 15);
|
|
data = FIELD_DP32(data, CPUCFG20, L3IU_SETS, 14);
|
|
data = FIELD_DP32(data, CPUCFG20, L3IU_SIZE, 6);
|
|
env->cpucfg[20] = data;
|
|
|
|
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
|
|
}
|
|
|
|
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
|
|
{
|
|
const char *typename = object_class_get_name(OBJECT_CLASS(data));
|
|
|
|
qemu_printf("%s\n", typename);
|
|
}
|
|
|
|
void loongarch_cpu_list(void)
|
|
{
|
|
GSList *list;
|
|
list = object_class_get_list_sorted(TYPE_LOONGARCH_CPU, false);
|
|
g_slist_foreach(list, loongarch_cpu_list_entry, NULL);
|
|
g_slist_free(list);
|
|
}
|
|
|
|
static void loongarch_cpu_reset(DeviceState *dev)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
|
|
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(cpu);
|
|
CPULoongArchState *env = &cpu->env;
|
|
|
|
lacc->parent_reset(dev);
|
|
|
|
env->fcsr0_mask = FCSR0_M1 | FCSR0_M2 | FCSR0_M3;
|
|
env->fcsr0 = 0x0;
|
|
|
|
int n;
|
|
/* Set csr registers value after reset */
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PLV, 0);
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, IE, 0);
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DA, 1);
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, PG, 0);
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATF, 1);
|
|
env->CSR_CRMD = FIELD_DP64(env->CSR_CRMD, CSR_CRMD, DATM, 1);
|
|
|
|
env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, FPE, 0);
|
|
env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, SXE, 0);
|
|
env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, ASXE, 0);
|
|
env->CSR_EUEN = FIELD_DP64(env->CSR_EUEN, CSR_EUEN, BTE, 0);
|
|
|
|
env->CSR_MISC = 0;
|
|
|
|
env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, VS, 0);
|
|
env->CSR_ECFG = FIELD_DP64(env->CSR_ECFG, CSR_ECFG, LIE, 0);
|
|
|
|
env->CSR_ESTAT = env->CSR_ESTAT & (~MAKE_64BIT_MASK(0, 2));
|
|
env->CSR_RVACFG = FIELD_DP64(env->CSR_RVACFG, CSR_RVACFG, RBITS, 0);
|
|
env->CSR_TCFG = FIELD_DP64(env->CSR_TCFG, CSR_TCFG, EN, 0);
|
|
env->CSR_LLBCTL = FIELD_DP64(env->CSR_LLBCTL, CSR_LLBCTL, KLO, 0);
|
|
env->CSR_TLBRERA = FIELD_DP64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR, 0);
|
|
env->CSR_MERRCTL = FIELD_DP64(env->CSR_MERRCTL, CSR_MERRCTL, ISMERR, 0);
|
|
|
|
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, TLB_TYPE, 2);
|
|
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, MTLB_ENTRY, 63);
|
|
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_WAYS, 7);
|
|
env->CSR_PRCFG3 = FIELD_DP64(env->CSR_PRCFG3, CSR_PRCFG3, STLB_SETS, 8);
|
|
|
|
for (n = 0; n < 4; n++) {
|
|
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV0, 0);
|
|
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV1, 0);
|
|
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV2, 0);
|
|
env->CSR_DMW[n] = FIELD_DP64(env->CSR_DMW[n], CSR_DMW, PLV3, 0);
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
env->pc = 0x1c000000;
|
|
memset(env->tlb, 0, sizeof(env->tlb));
|
|
#endif
|
|
|
|
restore_fp_status(env);
|
|
cs->exception_index = -1;
|
|
}
|
|
|
|
static void loongarch_cpu_disas_set_info(CPUState *s, disassemble_info *info)
|
|
{
|
|
info->print_insn = print_insn_loongarch;
|
|
}
|
|
|
|
static void loongarch_cpu_realizefn(DeviceState *dev, Error **errp)
|
|
{
|
|
CPUState *cs = CPU(dev);
|
|
LoongArchCPUClass *lacc = LOONGARCH_CPU_GET_CLASS(dev);
|
|
Error *local_err = NULL;
|
|
|
|
cpu_exec_realizefn(cs, &local_err);
|
|
if (local_err != NULL) {
|
|
error_propagate(errp, local_err);
|
|
return;
|
|
}
|
|
|
|
loongarch_cpu_register_gdb_regs_for_features(cs);
|
|
|
|
cpu_reset(cs);
|
|
qemu_init_vcpu(cs);
|
|
|
|
lacc->parent_realize(dev, errp);
|
|
}
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
static void loongarch_qemu_write(void *opaque, hwaddr addr,
|
|
uint64_t val, unsigned size)
|
|
{
|
|
}
|
|
|
|
static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size)
|
|
{
|
|
switch (addr) {
|
|
case FEATURE_REG:
|
|
return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI |
|
|
1ULL << IOCSRF_CSRIPI;
|
|
case VENDOR_REG:
|
|
return 0x6e6f73676e6f6f4cULL; /* "Loongson" */
|
|
case CPUNAME_REG:
|
|
return 0x303030354133ULL; /* "3A5000" */
|
|
case MISC_FUNC_REG:
|
|
return 1ULL << IOCSRM_EXTIOI_EN;
|
|
}
|
|
return 0ULL;
|
|
}
|
|
|
|
static const MemoryRegionOps loongarch_qemu_ops = {
|
|
.read = loongarch_qemu_read,
|
|
.write = loongarch_qemu_write,
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
.valid = {
|
|
.min_access_size = 4,
|
|
.max_access_size = 8,
|
|
},
|
|
.impl = {
|
|
.min_access_size = 8,
|
|
.max_access_size = 8,
|
|
},
|
|
};
|
|
#endif
|
|
|
|
static void loongarch_cpu_init(Object *obj)
|
|
{
|
|
LoongArchCPU *cpu = LOONGARCH_CPU(obj);
|
|
|
|
cpu_set_cpustate_pointers(cpu);
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
CPULoongArchState *env = &cpu->env;
|
|
qdev_init_gpio_in(DEVICE(cpu), loongarch_cpu_set_irq, N_IRQS);
|
|
timer_init_ns(&cpu->timer, QEMU_CLOCK_VIRTUAL,
|
|
&loongarch_constant_timer_cb, cpu);
|
|
memory_region_init_io(&env->system_iocsr, OBJECT(cpu), NULL,
|
|
env, "iocsr", UINT64_MAX);
|
|
address_space_init(&env->address_space_iocsr, &env->system_iocsr, "IOCSR");
|
|
memory_region_init_io(&env->iocsr_mem, OBJECT(cpu), &loongarch_qemu_ops,
|
|
NULL, "iocsr_misc", 0x428);
|
|
memory_region_add_subregion(&env->system_iocsr, 0, &env->iocsr_mem);
|
|
#endif
|
|
}
|
|
|
|
static ObjectClass *loongarch_cpu_class_by_name(const char *cpu_model)
|
|
{
|
|
ObjectClass *oc;
|
|
|
|
oc = object_class_by_name(cpu_model);
|
|
if (!oc) {
|
|
g_autofree char *typename
|
|
= g_strdup_printf(LOONGARCH_CPU_TYPE_NAME("%s"), cpu_model);
|
|
oc = object_class_by_name(typename);
|
|
if (!oc) {
|
|
return NULL;
|
|
}
|
|
}
|
|
|
|
if (object_class_dynamic_cast(oc, TYPE_LOONGARCH_CPU)
|
|
&& !object_class_is_abstract(oc)) {
|
|
return oc;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
void loongarch_cpu_dump_state(CPUState *cs, FILE *f, int flags)
|
|
{
|
|
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
|
|
CPULoongArchState *env = &cpu->env;
|
|
int i;
|
|
|
|
qemu_fprintf(f, " PC=%016" PRIx64 " ", env->pc);
|
|
qemu_fprintf(f, " FCSR0 0x%08x fp_status 0x%02x\n", env->fcsr0,
|
|
get_float_exception_flags(&env->fp_status));
|
|
|
|
/* gpr */
|
|
for (i = 0; i < 32; i++) {
|
|
if ((i & 3) == 0) {
|
|
qemu_fprintf(f, " GPR%02d:", i);
|
|
}
|
|
qemu_fprintf(f, " %s %016" PRIx64, regnames[i], env->gpr[i]);
|
|
if ((i & 3) == 3) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
|
|
qemu_fprintf(f, "CRMD=%016" PRIx64 "\n", env->CSR_CRMD);
|
|
qemu_fprintf(f, "PRMD=%016" PRIx64 "\n", env->CSR_PRMD);
|
|
qemu_fprintf(f, "EUEN=%016" PRIx64 "\n", env->CSR_EUEN);
|
|
qemu_fprintf(f, "ESTAT=%016" PRIx64 "\n", env->CSR_ESTAT);
|
|
qemu_fprintf(f, "ERA=%016" PRIx64 "\n", env->CSR_ERA);
|
|
qemu_fprintf(f, "BADV=%016" PRIx64 "\n", env->CSR_BADV);
|
|
qemu_fprintf(f, "BADI=%016" PRIx64 "\n", env->CSR_BADI);
|
|
qemu_fprintf(f, "EENTRY=%016" PRIx64 "\n", env->CSR_EENTRY);
|
|
qemu_fprintf(f, "PRCFG1=%016" PRIx64 ", PRCFG2=%016" PRIx64 ","
|
|
" PRCFG3=%016" PRIx64 "\n",
|
|
env->CSR_PRCFG1, env->CSR_PRCFG3, env->CSR_PRCFG3);
|
|
qemu_fprintf(f, "TLBRENTRY=%016" PRIx64 "\n", env->CSR_TLBRENTRY);
|
|
qemu_fprintf(f, "TLBRBADV=%016" PRIx64 "\n", env->CSR_TLBRBADV);
|
|
qemu_fprintf(f, "TLBRERA=%016" PRIx64 "\n", env->CSR_TLBRERA);
|
|
|
|
/* fpr */
|
|
if (flags & CPU_DUMP_FPU) {
|
|
for (i = 0; i < 32; i++) {
|
|
qemu_fprintf(f, " %s %016" PRIx64, fregnames[i], env->fpr[i]);
|
|
if ((i & 3) == 3) {
|
|
qemu_fprintf(f, "\n");
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_TCG
|
|
#include "hw/core/tcg-cpu-ops.h"
|
|
|
|
static struct TCGCPUOps loongarch_tcg_ops = {
|
|
.initialize = loongarch_translate_init,
|
|
.synchronize_from_tb = loongarch_cpu_synchronize_from_tb,
|
|
.restore_state_to_opc = loongarch_restore_state_to_opc,
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
.tlb_fill = loongarch_cpu_tlb_fill,
|
|
.cpu_exec_interrupt = loongarch_cpu_exec_interrupt,
|
|
.do_interrupt = loongarch_cpu_do_interrupt,
|
|
.do_transaction_failed = loongarch_cpu_do_transaction_failed,
|
|
#endif
|
|
};
|
|
#endif /* CONFIG_TCG */
|
|
|
|
#ifndef CONFIG_USER_ONLY
|
|
#include "hw/core/sysemu-cpu-ops.h"
|
|
|
|
static const struct SysemuCPUOps loongarch_sysemu_ops = {
|
|
.get_phys_page_debug = loongarch_cpu_get_phys_page_debug,
|
|
};
|
|
#endif
|
|
|
|
static gchar *loongarch_gdb_arch_name(CPUState *cs)
|
|
{
|
|
return g_strdup("loongarch64");
|
|
}
|
|
|
|
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
|
|
{
|
|
LoongArchCPUClass *lacc = LOONGARCH_CPU_CLASS(c);
|
|
CPUClass *cc = CPU_CLASS(c);
|
|
DeviceClass *dc = DEVICE_CLASS(c);
|
|
|
|
device_class_set_parent_realize(dc, loongarch_cpu_realizefn,
|
|
&lacc->parent_realize);
|
|
device_class_set_parent_reset(dc, loongarch_cpu_reset, &lacc->parent_reset);
|
|
|
|
cc->class_by_name = loongarch_cpu_class_by_name;
|
|
cc->has_work = loongarch_cpu_has_work;
|
|
cc->dump_state = loongarch_cpu_dump_state;
|
|
cc->set_pc = loongarch_cpu_set_pc;
|
|
cc->get_pc = loongarch_cpu_get_pc;
|
|
#ifndef CONFIG_USER_ONLY
|
|
dc->vmsd = &vmstate_loongarch_cpu;
|
|
cc->sysemu_ops = &loongarch_sysemu_ops;
|
|
#endif
|
|
cc->disas_set_info = loongarch_cpu_disas_set_info;
|
|
cc->gdb_read_register = loongarch_cpu_gdb_read_register;
|
|
cc->gdb_write_register = loongarch_cpu_gdb_write_register;
|
|
cc->disas_set_info = loongarch_cpu_disas_set_info;
|
|
cc->gdb_num_core_regs = 35;
|
|
cc->gdb_core_xml_file = "loongarch-base64.xml";
|
|
cc->gdb_stop_before_watchpoint = true;
|
|
cc->gdb_arch_name = loongarch_gdb_arch_name;
|
|
|
|
#ifdef CONFIG_TCG
|
|
cc->tcg_ops = &loongarch_tcg_ops;
|
|
#endif
|
|
}
|
|
|
|
#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
|
|
{ \
|
|
.parent = TYPE_LOONGARCH_CPU, \
|
|
.instance_init = initfn, \
|
|
.name = LOONGARCH_CPU_TYPE_NAME(model), \
|
|
}
|
|
|
|
static const TypeInfo loongarch_cpu_type_infos[] = {
|
|
{
|
|
.name = TYPE_LOONGARCH_CPU,
|
|
.parent = TYPE_CPU,
|
|
.instance_size = sizeof(LoongArchCPU),
|
|
.instance_init = loongarch_cpu_init,
|
|
|
|
.abstract = true,
|
|
.class_size = sizeof(LoongArchCPUClass),
|
|
.class_init = loongarch_cpu_class_init,
|
|
},
|
|
DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
|
|
};
|
|
|
|
DEFINE_TYPES(loongarch_cpu_type_infos)
|
|
|
|
static void loongarch_cpu_add_definition(gpointer data, gpointer user_data)
|
|
{
|
|
ObjectClass *oc = data;
|
|
CpuDefinitionInfoList **cpu_list = user_data;
|
|
CpuDefinitionInfo *info = g_new0(CpuDefinitionInfo, 1);
|
|
const char *typename = object_class_get_name(oc);
|
|
|
|
info->name = g_strndup(typename,
|
|
strlen(typename) - strlen("-" TYPE_LOONGARCH_CPU));
|
|
info->q_typename = g_strdup(typename);
|
|
|
|
QAPI_LIST_PREPEND(*cpu_list, info);
|
|
}
|
|
|
|
CpuDefinitionInfoList *qmp_query_cpu_definitions(Error **errp)
|
|
{
|
|
CpuDefinitionInfoList *cpu_list = NULL;
|
|
GSList *list;
|
|
|
|
list = object_class_get_list(TYPE_LOONGARCH_CPU, false);
|
|
g_slist_foreach(list, loongarch_cpu_add_definition, &cpu_list);
|
|
g_slist_free(list);
|
|
|
|
return cpu_list;
|
|
}
|