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789 lines
24 KiB
C
789 lines
24 KiB
C
/*
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* ARM translation: M-profile NOCP special-case instructions
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*
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* Copyright (c) 2020 Linaro, Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "tcg/tcg-op.h"
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#include "tcg/tcg-op-gvec.h"
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#include "translate.h"
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#include "translate-a32.h"
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#include "decode-m-nocp.c.inc"
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/*
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* Decode VLLDM and VLSTM are nonstandard because:
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* * if there is no FPU then these insns must NOP in
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* Secure state and UNDEF in Nonsecure state
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* * if there is an FPU then these insns do not have
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* the usual behaviour that vfp_access_check() provides of
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* being controlled by CPACR/NSACR enable bits or the
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* lazy-stacking logic.
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*/
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static bool trans_VLLDM_VLSTM(DisasContext *s, arg_VLLDM_VLSTM *a)
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{
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TCGv_i32 fptr;
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if (!arm_dc_feature(s, ARM_FEATURE_M) ||
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!arm_dc_feature(s, ARM_FEATURE_V8)) {
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return false;
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}
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if (a->op) {
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/*
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* T2 encoding ({D0-D31} reglist): v8.1M and up. We choose not
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* to take the IMPDEF option to make memory accesses to the stack
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* slots that correspond to the D16-D31 registers (discarding
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* read data and writing UNKNOWN values), so for us the T2
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* encoding behaves identically to the T1 encoding.
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*/
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return false;
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}
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} else {
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/*
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* T1 encoding ({D0-D15} reglist); undef if we have 32 Dregs.
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* This is currently architecturally impossible, but we add the
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* check to stay in line with the pseudocode. Note that we must
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* emit code for the UNDEF so it takes precedence over the NOCP.
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*/
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if (dc_isar_feature(aa32_simd_r32, s)) {
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unallocated_encoding(s);
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return true;
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}
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}
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/*
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* If not secure, UNDEF. We must emit code for this
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* rather than returning false so that this takes
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* precedence over the m-nocp.decode NOCP fallback.
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*/
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if (!s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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s->eci_handled = true;
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/* If no fpu, NOP. */
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if (!dc_isar_feature(aa32_vfp, s)) {
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clear_eci_state(s);
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return true;
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}
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fptr = load_reg(s, a->rn);
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if (a->l) {
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gen_helper_v7m_vlldm(cpu_env, fptr);
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} else {
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gen_helper_v7m_vlstm(cpu_env, fptr);
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}
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tcg_temp_free_i32(fptr);
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clear_eci_state(s);
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/*
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* End the TB, because we have updated FP control bits,
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* and possibly VPR or LTPSIZE.
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*/
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s->base.is_jmp = DISAS_UPDATE_EXIT;
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return true;
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}
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static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM *a)
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{
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int btmreg, topreg;
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TCGv_i64 zero;
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TCGv_i32 aspen, sfpa;
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if (!dc_isar_feature(aa32_m_sec_state, s)) {
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/* Before v8.1M, fall through in decode to NOCP check */
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return false;
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}
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/* Explicitly UNDEF because this takes precedence over NOCP */
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if (!arm_dc_feature(s, ARM_FEATURE_M_MAIN) || !s->v8m_secure) {
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unallocated_encoding(s);
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return true;
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}
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s->eci_handled = true;
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if (!dc_isar_feature(aa32_vfp_simd, s)) {
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/* NOP if we have neither FP nor MVE */
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clear_eci_state(s);
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return true;
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}
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/*
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* If FPCCR.ASPEN != 0 && CONTROL_S.SFPA == 0 then there is no
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* active floating point context so we must NOP (without doing
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* any lazy state preservation or the NOCP check).
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*/
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aspen = load_cpu_field(v7m.fpccr[M_REG_S]);
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sfpa = load_cpu_field(v7m.control[M_REG_S]);
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tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_andi_i32(sfpa, sfpa, R_V7M_CONTROL_SFPA_MASK);
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tcg_gen_or_i32(sfpa, sfpa, aspen);
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arm_gen_condlabel(s);
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tcg_gen_brcondi_i32(TCG_COND_EQ, sfpa, 0, s->condlabel.label);
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if (s->fp_excp_el != 0) {
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gen_exception_insn_el(s, 0, EXCP_NOCP,
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syn_uncategorized(), s->fp_excp_el);
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return true;
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}
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topreg = a->vd + a->imm - 1;
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btmreg = a->vd;
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/* Convert to Sreg numbers if the insn specified in Dregs */
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if (a->size == 3) {
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topreg = topreg * 2 + 1;
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btmreg *= 2;
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}
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if (topreg > 63 || (topreg > 31 && !(topreg & 1))) {
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/* UNPREDICTABLE: we choose to undef */
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unallocated_encoding(s);
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return true;
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}
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/* Silently ignore requests to clear D16-D31 if they don't exist */
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if (topreg > 31 && !dc_isar_feature(aa32_simd_r32, s)) {
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topreg = 31;
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}
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if (!vfp_access_check(s)) {
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return true;
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}
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/* Zero the Sregs from btmreg to topreg inclusive. */
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zero = tcg_constant_i64(0);
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if (btmreg & 1) {
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write_neon_element64(zero, btmreg >> 1, 1, MO_32);
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btmreg++;
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}
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for (; btmreg + 1 <= topreg; btmreg += 2) {
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write_neon_element64(zero, btmreg >> 1, 0, MO_64);
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}
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if (btmreg == topreg) {
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write_neon_element64(zero, btmreg >> 1, 0, MO_32);
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btmreg++;
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}
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assert(btmreg == topreg + 1);
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if (dc_isar_feature(aa32_mve, s)) {
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store_cpu_field(tcg_constant_i32(0), v7m.vpr);
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}
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clear_eci_state(s);
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return true;
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}
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/*
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* M-profile provides two different sets of instructions that can
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* access floating point system registers: VMSR/VMRS (which move
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* to/from a general purpose register) and VLDR/VSTR sysreg (which
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* move directly to/from memory). In some cases there are also side
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* effects which must happen after any write to memory (which could
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* cause an exception). So we implement the common logic for the
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* sysreg access in gen_M_fp_sysreg_write() and gen_M_fp_sysreg_read(),
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* which take pointers to callback functions which will perform the
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* actual "read/write general purpose register" and "read/write
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* memory" operations.
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*/
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/*
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* Emit code to store the sysreg to its final destination; frees the
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* TCG temp 'value' it is passed. do_access is true to do the store,
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* and false to skip it and only perform side-effects like base
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* register writeback.
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*/
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typedef void fp_sysreg_storefn(DisasContext *s, void *opaque, TCGv_i32 value,
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bool do_access);
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/*
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* Emit code to load the value to be copied to the sysreg; returns
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* a new TCG temporary. do_access is true to do the store,
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* and false to skip it and only perform side-effects like base
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* register writeback.
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*/
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typedef TCGv_i32 fp_sysreg_loadfn(DisasContext *s, void *opaque,
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bool do_access);
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/* Common decode/access checks for fp sysreg read/write */
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typedef enum FPSysRegCheckResult {
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FPSysRegCheckFailed, /* caller should return false */
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FPSysRegCheckDone, /* caller should return true */
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FPSysRegCheckContinue, /* caller should continue generating code */
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} FPSysRegCheckResult;
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static FPSysRegCheckResult fp_sysreg_checks(DisasContext *s, int regno)
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{
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if (!dc_isar_feature(aa32_fpsp_v2, s) && !dc_isar_feature(aa32_mve, s)) {
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return FPSysRegCheckFailed;
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}
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switch (regno) {
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case ARM_VFP_FPSCR:
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case QEMU_VFP_FPSCR_NZCV:
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break;
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case ARM_VFP_FPSCR_NZCVQC:
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return FPSysRegCheckFailed;
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}
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break;
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case ARM_VFP_FPCXT_S:
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case ARM_VFP_FPCXT_NS:
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if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
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return FPSysRegCheckFailed;
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}
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if (!s->v8m_secure) {
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return FPSysRegCheckFailed;
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}
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break;
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case ARM_VFP_VPR:
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case ARM_VFP_P0:
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if (!dc_isar_feature(aa32_mve, s)) {
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return FPSysRegCheckFailed;
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}
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break;
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default:
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return FPSysRegCheckFailed;
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}
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/*
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* FPCXT_NS is a special case: it has specific handling for
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* "current FP state is inactive", and must do the PreserveFPState()
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* but not the usual full set of actions done by ExecuteFPCheck().
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* So we don't call vfp_access_check() and the callers must handle this.
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*/
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if (regno != ARM_VFP_FPCXT_NS && !vfp_access_check(s)) {
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return FPSysRegCheckDone;
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}
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return FPSysRegCheckContinue;
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}
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static void gen_branch_fpInactive(DisasContext *s, TCGCond cond,
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TCGLabel *label)
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{
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/*
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* FPCXT_NS is a special case: it has specific handling for
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* "current FP state is inactive", and must do the PreserveFPState()
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* but not the usual full set of actions done by ExecuteFPCheck().
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* We don't have a TB flag that matches the fpInactive check, so we
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* do it at runtime as we don't expect FPCXT_NS accesses to be frequent.
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*
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* Emit code that checks fpInactive and does a conditional
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* branch to label based on it:
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* if cond is TCG_COND_NE then branch if fpInactive != 0 (ie if inactive)
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* if cond is TCG_COND_EQ then branch if fpInactive == 0 (ie if active)
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*/
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assert(cond == TCG_COND_EQ || cond == TCG_COND_NE);
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/* fpInactive = FPCCR_NS.ASPEN == 1 && CONTROL.FPCA == 0 */
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TCGv_i32 aspen, fpca;
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aspen = load_cpu_field(v7m.fpccr[M_REG_NS]);
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fpca = load_cpu_field(v7m.control[M_REG_S]);
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tcg_gen_andi_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_xori_i32(aspen, aspen, R_V7M_FPCCR_ASPEN_MASK);
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tcg_gen_andi_i32(fpca, fpca, R_V7M_CONTROL_FPCA_MASK);
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tcg_gen_or_i32(fpca, fpca, aspen);
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tcg_gen_brcondi_i32(tcg_invert_cond(cond), fpca, 0, label);
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tcg_temp_free_i32(aspen);
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tcg_temp_free_i32(fpca);
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}
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static bool gen_M_fp_sysreg_write(DisasContext *s, int regno,
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fp_sysreg_loadfn *loadfn,
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void *opaque)
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{
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/* Do a write to an M-profile floating point system register */
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TCGv_i32 tmp;
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TCGLabel *lab_end = NULL;
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switch (fp_sysreg_checks(s, regno)) {
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case FPSysRegCheckFailed:
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return false;
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case FPSysRegCheckDone:
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return true;
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case FPSysRegCheckContinue:
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break;
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}
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switch (regno) {
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case ARM_VFP_FPSCR:
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tmp = loadfn(s, opaque, true);
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gen_helper_vfp_set_fpscr(cpu_env, tmp);
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tcg_temp_free_i32(tmp);
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gen_lookup_tb(s);
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break;
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case ARM_VFP_FPSCR_NZCVQC:
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{
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TCGv_i32 fpscr;
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tmp = loadfn(s, opaque, true);
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if (dc_isar_feature(aa32_mve, s)) {
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/* QC is only present for MVE; otherwise RES0 */
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TCGv_i32 qc = tcg_temp_new_i32();
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tcg_gen_andi_i32(qc, tmp, FPCR_QC);
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/*
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* The 4 vfp.qc[] fields need only be "zero" vs "non-zero";
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* here writing the same value into all elements is simplest.
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*/
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tcg_gen_gvec_dup_i32(MO_32, offsetof(CPUARMState, vfp.qc),
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16, 16, qc);
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}
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tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
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fpscr = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
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tcg_gen_andi_i32(fpscr, fpscr, ~FPCR_NZCV_MASK);
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tcg_gen_or_i32(fpscr, fpscr, tmp);
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store_cpu_field(fpscr, vfp.xregs[ARM_VFP_FPSCR]);
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tcg_temp_free_i32(tmp);
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break;
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}
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case ARM_VFP_FPCXT_NS:
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{
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TCGLabel *lab_active = gen_new_label();
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lab_end = gen_new_label();
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gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
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/*
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* fpInactive case: write is a NOP, so only do side effects
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* like register writeback before we branch to end
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*/
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loadfn(s, opaque, false);
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tcg_gen_br(lab_end);
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gen_set_label(lab_active);
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/*
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* !fpInactive: if FPU disabled, take NOCP exception;
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* otherwise PreserveFPState(), and then FPCXT_NS writes
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* behave the same as FPCXT_S writes.
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*/
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if (!vfp_access_check_m(s, true)) {
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/*
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* This was only a conditional exception, so override
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* gen_exception_insn_el()'s default to DISAS_NORETURN
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*/
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s->base.is_jmp = DISAS_NEXT;
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break;
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}
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}
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/* fall through */
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case ARM_VFP_FPCXT_S:
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{
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TCGv_i32 sfpa, control;
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/*
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* Set FPSCR and CONTROL.SFPA from value; the new FPSCR takes
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* bits [27:0] from value and zeroes bits [31:28].
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*/
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tmp = loadfn(s, opaque, true);
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sfpa = tcg_temp_new_i32();
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tcg_gen_shri_i32(sfpa, tmp, 31);
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control = load_cpu_field(v7m.control[M_REG_S]);
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tcg_gen_deposit_i32(control, control, sfpa,
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R_V7M_CONTROL_SFPA_SHIFT, 1);
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store_cpu_field(control, v7m.control[M_REG_S]);
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tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
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gen_helper_vfp_set_fpscr(cpu_env, tmp);
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s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
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tcg_temp_free_i32(tmp);
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tcg_temp_free_i32(sfpa);
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break;
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}
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case ARM_VFP_VPR:
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/* Behaves as NOP if not privileged */
|
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if (IS_USER(s)) {
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loadfn(s, opaque, false);
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break;
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}
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tmp = loadfn(s, opaque, true);
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store_cpu_field(tmp, v7m.vpr);
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s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
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break;
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case ARM_VFP_P0:
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{
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TCGv_i32 vpr;
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tmp = loadfn(s, opaque, true);
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vpr = load_cpu_field(v7m.vpr);
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tcg_gen_deposit_i32(vpr, vpr, tmp,
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R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
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store_cpu_field(vpr, v7m.vpr);
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s->base.is_jmp = DISAS_UPDATE_NOCHAIN;
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tcg_temp_free_i32(tmp);
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break;
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}
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default:
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g_assert_not_reached();
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}
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if (lab_end) {
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gen_set_label(lab_end);
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}
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return true;
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}
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static bool gen_M_fp_sysreg_read(DisasContext *s, int regno,
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fp_sysreg_storefn *storefn,
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void *opaque)
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{
|
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/* Do a read from an M-profile floating point system register */
|
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TCGv_i32 tmp;
|
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TCGLabel *lab_end = NULL;
|
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bool lookup_tb = false;
|
|
|
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switch (fp_sysreg_checks(s, regno)) {
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case FPSysRegCheckFailed:
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return false;
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case FPSysRegCheckDone:
|
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return true;
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case FPSysRegCheckContinue:
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break;
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}
|
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|
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if (regno == ARM_VFP_FPSCR_NZCVQC && !dc_isar_feature(aa32_mve, s)) {
|
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/* QC is RES0 without MVE, so NZCVQC simplifies to NZCV */
|
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regno = QEMU_VFP_FPSCR_NZCV;
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}
|
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|
|
switch (regno) {
|
|
case ARM_VFP_FPSCR:
|
|
tmp = tcg_temp_new_i32();
|
|
gen_helper_vfp_get_fpscr(tmp, cpu_env);
|
|
storefn(s, opaque, tmp, true);
|
|
break;
|
|
case ARM_VFP_FPSCR_NZCVQC:
|
|
tmp = tcg_temp_new_i32();
|
|
gen_helper_vfp_get_fpscr(tmp, cpu_env);
|
|
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCVQC_MASK);
|
|
storefn(s, opaque, tmp, true);
|
|
break;
|
|
case QEMU_VFP_FPSCR_NZCV:
|
|
/*
|
|
* Read just NZCV; this is a special case to avoid the
|
|
* helper call for the "VMRS to CPSR.NZCV" insn.
|
|
*/
|
|
tmp = load_cpu_field(vfp.xregs[ARM_VFP_FPSCR]);
|
|
tcg_gen_andi_i32(tmp, tmp, FPCR_NZCV_MASK);
|
|
storefn(s, opaque, tmp, true);
|
|
break;
|
|
case ARM_VFP_FPCXT_S:
|
|
{
|
|
TCGv_i32 control, sfpa, fpscr;
|
|
/* Bits [27:0] from FPSCR, bit [31] from CONTROL.SFPA */
|
|
tmp = tcg_temp_new_i32();
|
|
sfpa = tcg_temp_new_i32();
|
|
gen_helper_vfp_get_fpscr(tmp, cpu_env);
|
|
tcg_gen_andi_i32(tmp, tmp, ~FPCR_NZCV_MASK);
|
|
control = load_cpu_field(v7m.control[M_REG_S]);
|
|
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
|
|
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
|
|
tcg_gen_or_i32(tmp, tmp, sfpa);
|
|
tcg_temp_free_i32(sfpa);
|
|
/*
|
|
* Store result before updating FPSCR etc, in case
|
|
* it is a memory write which causes an exception.
|
|
*/
|
|
storefn(s, opaque, tmp, true);
|
|
/*
|
|
* Now we must reset FPSCR from FPDSCR_NS, and clear
|
|
* CONTROL.SFPA; so we'll end the TB here.
|
|
*/
|
|
tcg_gen_andi_i32(control, control, ~R_V7M_CONTROL_SFPA_MASK);
|
|
store_cpu_field(control, v7m.control[M_REG_S]);
|
|
fpscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
|
|
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
|
|
tcg_temp_free_i32(fpscr);
|
|
lookup_tb = true;
|
|
break;
|
|
}
|
|
case ARM_VFP_FPCXT_NS:
|
|
{
|
|
TCGv_i32 control, sfpa, fpscr, fpdscr;
|
|
TCGLabel *lab_active = gen_new_label();
|
|
|
|
lookup_tb = true;
|
|
|
|
gen_branch_fpInactive(s, TCG_COND_EQ, lab_active);
|
|
/* fpInactive case: reads as FPDSCR_NS */
|
|
TCGv_i32 tmp = load_cpu_field(v7m.fpdscr[M_REG_NS]);
|
|
storefn(s, opaque, tmp, true);
|
|
lab_end = gen_new_label();
|
|
tcg_gen_br(lab_end);
|
|
|
|
gen_set_label(lab_active);
|
|
/*
|
|
* !fpInactive: if FPU disabled, take NOCP exception;
|
|
* otherwise PreserveFPState(), and then FPCXT_NS
|
|
* reads the same as FPCXT_S.
|
|
*/
|
|
if (!vfp_access_check_m(s, true)) {
|
|
/*
|
|
* This was only a conditional exception, so override
|
|
* gen_exception_insn_el()'s default to DISAS_NORETURN
|
|
*/
|
|
s->base.is_jmp = DISAS_NEXT;
|
|
break;
|
|
}
|
|
tmp = tcg_temp_new_i32();
|
|
sfpa = tcg_temp_new_i32();
|
|
fpscr = tcg_temp_new_i32();
|
|
gen_helper_vfp_get_fpscr(fpscr, cpu_env);
|
|
tcg_gen_andi_i32(tmp, fpscr, ~FPCR_NZCV_MASK);
|
|
control = load_cpu_field(v7m.control[M_REG_S]);
|
|
tcg_gen_andi_i32(sfpa, control, R_V7M_CONTROL_SFPA_MASK);
|
|
tcg_gen_shli_i32(sfpa, sfpa, 31 - R_V7M_CONTROL_SFPA_SHIFT);
|
|
tcg_gen_or_i32(tmp, tmp, sfpa);
|
|
tcg_temp_free_i32(control);
|
|
/* Store result before updating FPSCR, in case it faults */
|
|
storefn(s, opaque, tmp, true);
|
|
/* If SFPA is zero then set FPSCR from FPDSCR_NS */
|
|
fpdscr = load_cpu_field(v7m.fpdscr[M_REG_NS]);
|
|
tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0),
|
|
fpdscr, fpscr);
|
|
gen_helper_vfp_set_fpscr(cpu_env, fpscr);
|
|
tcg_temp_free_i32(sfpa);
|
|
tcg_temp_free_i32(fpdscr);
|
|
tcg_temp_free_i32(fpscr);
|
|
break;
|
|
}
|
|
case ARM_VFP_VPR:
|
|
/* Behaves as NOP if not privileged */
|
|
if (IS_USER(s)) {
|
|
storefn(s, opaque, NULL, false);
|
|
break;
|
|
}
|
|
tmp = load_cpu_field(v7m.vpr);
|
|
storefn(s, opaque, tmp, true);
|
|
break;
|
|
case ARM_VFP_P0:
|
|
tmp = load_cpu_field(v7m.vpr);
|
|
tcg_gen_extract_i32(tmp, tmp, R_V7M_VPR_P0_SHIFT, R_V7M_VPR_P0_LENGTH);
|
|
storefn(s, opaque, tmp, true);
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
if (lab_end) {
|
|
gen_set_label(lab_end);
|
|
}
|
|
if (lookup_tb) {
|
|
gen_lookup_tb(s);
|
|
}
|
|
return true;
|
|
}
|
|
|
|
static void fp_sysreg_to_gpr(DisasContext *s, void *opaque, TCGv_i32 value,
|
|
bool do_access)
|
|
{
|
|
arg_VMSR_VMRS *a = opaque;
|
|
|
|
if (!do_access) {
|
|
return;
|
|
}
|
|
|
|
if (a->rt == 15) {
|
|
/* Set the 4 flag bits in the CPSR */
|
|
gen_set_nzcv(value);
|
|
tcg_temp_free_i32(value);
|
|
} else {
|
|
store_reg(s, a->rt, value);
|
|
}
|
|
}
|
|
|
|
static TCGv_i32 gpr_to_fp_sysreg(DisasContext *s, void *opaque, bool do_access)
|
|
{
|
|
arg_VMSR_VMRS *a = opaque;
|
|
|
|
if (!do_access) {
|
|
return NULL;
|
|
}
|
|
return load_reg(s, a->rt);
|
|
}
|
|
|
|
static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR_VMRS *a)
|
|
{
|
|
/*
|
|
* Accesses to R15 are UNPREDICTABLE; we choose to undef.
|
|
* FPSCR -> r15 is a special case which writes to the PSR flags;
|
|
* set a->reg to a special value to tell gen_M_fp_sysreg_read()
|
|
* we only care about the top 4 bits of FPSCR there.
|
|
*/
|
|
if (a->rt == 15) {
|
|
if (a->l && a->reg == ARM_VFP_FPSCR) {
|
|
a->reg = QEMU_VFP_FPSCR_NZCV;
|
|
} else {
|
|
return false;
|
|
}
|
|
}
|
|
|
|
if (a->l) {
|
|
/* VMRS, move FP system register to gp register */
|
|
return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_gpr, a);
|
|
} else {
|
|
/* VMSR, move gp register to FP system register */
|
|
return gen_M_fp_sysreg_write(s, a->reg, gpr_to_fp_sysreg, a);
|
|
}
|
|
}
|
|
|
|
static void fp_sysreg_to_memory(DisasContext *s, void *opaque, TCGv_i32 value,
|
|
bool do_access)
|
|
{
|
|
arg_vldr_sysreg *a = opaque;
|
|
uint32_t offset = a->imm;
|
|
TCGv_i32 addr;
|
|
|
|
if (!a->a) {
|
|
offset = -offset;
|
|
}
|
|
|
|
if (!do_access && !a->w) {
|
|
return;
|
|
}
|
|
|
|
addr = load_reg(s, a->rn);
|
|
if (a->p) {
|
|
tcg_gen_addi_i32(addr, addr, offset);
|
|
}
|
|
|
|
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
|
|
gen_helper_v8m_stackcheck(cpu_env, addr);
|
|
}
|
|
|
|
if (do_access) {
|
|
gen_aa32_st_i32(s, value, addr, get_mem_index(s),
|
|
MO_UL | MO_ALIGN | s->be_data);
|
|
tcg_temp_free_i32(value);
|
|
}
|
|
|
|
if (a->w) {
|
|
/* writeback */
|
|
if (!a->p) {
|
|
tcg_gen_addi_i32(addr, addr, offset);
|
|
}
|
|
store_reg(s, a->rn, addr);
|
|
} else {
|
|
tcg_temp_free_i32(addr);
|
|
}
|
|
}
|
|
|
|
static TCGv_i32 memory_to_fp_sysreg(DisasContext *s, void *opaque,
|
|
bool do_access)
|
|
{
|
|
arg_vldr_sysreg *a = opaque;
|
|
uint32_t offset = a->imm;
|
|
TCGv_i32 addr;
|
|
TCGv_i32 value = NULL;
|
|
|
|
if (!a->a) {
|
|
offset = -offset;
|
|
}
|
|
|
|
if (!do_access && !a->w) {
|
|
return NULL;
|
|
}
|
|
|
|
addr = load_reg(s, a->rn);
|
|
if (a->p) {
|
|
tcg_gen_addi_i32(addr, addr, offset);
|
|
}
|
|
|
|
if (s->v8m_stackcheck && a->rn == 13 && a->w) {
|
|
gen_helper_v8m_stackcheck(cpu_env, addr);
|
|
}
|
|
|
|
if (do_access) {
|
|
value = tcg_temp_new_i32();
|
|
gen_aa32_ld_i32(s, value, addr, get_mem_index(s),
|
|
MO_UL | MO_ALIGN | s->be_data);
|
|
}
|
|
|
|
if (a->w) {
|
|
/* writeback */
|
|
if (!a->p) {
|
|
tcg_gen_addi_i32(addr, addr, offset);
|
|
}
|
|
store_reg(s, a->rn, addr);
|
|
} else {
|
|
tcg_temp_free_i32(addr);
|
|
}
|
|
return value;
|
|
}
|
|
|
|
static bool trans_VLDR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
|
|
{
|
|
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
|
|
return false;
|
|
}
|
|
if (a->rn == 15) {
|
|
return false;
|
|
}
|
|
return gen_M_fp_sysreg_write(s, a->reg, memory_to_fp_sysreg, a);
|
|
}
|
|
|
|
static bool trans_VSTR_sysreg(DisasContext *s, arg_vldr_sysreg *a)
|
|
{
|
|
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
|
|
return false;
|
|
}
|
|
if (a->rn == 15) {
|
|
return false;
|
|
}
|
|
return gen_M_fp_sysreg_read(s, a->reg, fp_sysreg_to_memory, a);
|
|
}
|
|
|
|
static bool trans_NOCP(DisasContext *s, arg_nocp *a)
|
|
{
|
|
/*
|
|
* Handle M-profile early check for disabled coprocessor:
|
|
* all we need to do here is emit the NOCP exception if
|
|
* the coprocessor is disabled. Otherwise we return false
|
|
* and the real VFP/etc decode will handle the insn.
|
|
*/
|
|
assert(arm_dc_feature(s, ARM_FEATURE_M));
|
|
|
|
if (a->cp == 11) {
|
|
a->cp = 10;
|
|
}
|
|
if (arm_dc_feature(s, ARM_FEATURE_V8_1M) &&
|
|
(a->cp == 8 || a->cp == 9 || a->cp == 14 || a->cp == 15)) {
|
|
/* in v8.1M cp 8, 9, 14, 15 also are governed by the cp10 enable */
|
|
a->cp = 10;
|
|
}
|
|
|
|
if (a->cp != 10) {
|
|
gen_exception_insn(s, 0, EXCP_NOCP, syn_uncategorized());
|
|
return true;
|
|
}
|
|
|
|
if (s->fp_excp_el != 0) {
|
|
gen_exception_insn_el(s, 0, EXCP_NOCP,
|
|
syn_uncategorized(), s->fp_excp_el);
|
|
return true;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool trans_NOCP_8_1(DisasContext *s, arg_nocp *a)
|
|
{
|
|
/* This range needs a coprocessor check for v8.1M and later only */
|
|
if (!arm_dc_feature(s, ARM_FEATURE_V8_1M)) {
|
|
return false;
|
|
}
|
|
return trans_NOCP(s, a);
|
|
}
|