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317 lines
11 KiB
C
317 lines
11 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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#include "elf.h"
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#include "internal.h"
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#include "fpu_helper.h"
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# ifdef TARGET_ABI_MIPSO32
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# define MIPS_SYSCALL_NUMBER_UNUSED -1
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static const int8_t mips_syscall_args[] = {
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#include "syscall-args-o32.c.inc"
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};
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# endif /* O32 */
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/* Break codes */
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enum {
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BRK_OVERFLOW = 6,
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BRK_DIVZERO = 7
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};
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static void do_tr_or_bp(CPUMIPSState *env, unsigned int code, bool trap)
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{
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target_ulong pc = env->active_tc.PC;
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switch (code) {
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case BRK_OVERFLOW:
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force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, pc);
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break;
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case BRK_DIVZERO:
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force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, pc);
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break;
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default:
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if (trap) {
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force_sig(TARGET_SIGTRAP);
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} else {
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, pc);
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}
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break;
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}
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}
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void cpu_loop(CPUMIPSState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr, si_code;
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unsigned int code;
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abi_long ret;
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# ifdef TARGET_ABI_MIPSO32
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unsigned int syscall_num;
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# endif
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for(;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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case EXCP_SYSCALL:
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env->active_tc.PC += 4;
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# ifdef TARGET_ABI_MIPSO32
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syscall_num = env->active_tc.gpr[2] - 4000;
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if (syscall_num >= sizeof(mips_syscall_args)) {
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/* syscall_num is larger that any defined for MIPS O32 */
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ret = -TARGET_ENOSYS;
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} else if (mips_syscall_args[syscall_num] ==
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MIPS_SYSCALL_NUMBER_UNUSED) {
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/* syscall_num belongs to the range not defined for MIPS O32 */
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ret = -TARGET_ENOSYS;
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} else {
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/* syscall_num is valid */
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int nb_args;
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abi_ulong sp_reg;
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abi_ulong arg5 = 0, arg6 = 0, arg7 = 0, arg8 = 0;
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nb_args = mips_syscall_args[syscall_num];
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sp_reg = env->active_tc.gpr[29];
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switch (nb_args) {
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/* these arguments are taken from the stack */
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case 8:
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if ((ret = get_user_ual(arg8, sp_reg + 28)) != 0) {
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goto done_syscall;
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}
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/* fall through */
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case 7:
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if ((ret = get_user_ual(arg7, sp_reg + 24)) != 0) {
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goto done_syscall;
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}
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/* fall through */
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case 6:
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if ((ret = get_user_ual(arg6, sp_reg + 20)) != 0) {
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goto done_syscall;
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}
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/* fall through */
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case 5:
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if ((ret = get_user_ual(arg5, sp_reg + 16)) != 0) {
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goto done_syscall;
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}
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/* fall through */
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default:
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break;
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}
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ret = do_syscall(env, env->active_tc.gpr[2],
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env->active_tc.gpr[4],
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env->active_tc.gpr[5],
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env->active_tc.gpr[6],
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env->active_tc.gpr[7],
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arg5, arg6, arg7, arg8);
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}
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done_syscall:
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# else
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ret = do_syscall(env, env->active_tc.gpr[2],
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env->active_tc.gpr[4], env->active_tc.gpr[5],
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env->active_tc.gpr[6], env->active_tc.gpr[7],
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env->active_tc.gpr[8], env->active_tc.gpr[9],
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env->active_tc.gpr[10], env->active_tc.gpr[11]);
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# endif /* O32 */
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if (ret == -QEMU_ERESTARTSYS) {
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env->active_tc.PC -= 4;
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break;
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}
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if (ret == -QEMU_ESIGRETURN) {
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/* Returning from a successful sigreturn syscall.
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Avoid clobbering register state. */
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break;
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}
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if ((abi_ulong)ret >= (abi_ulong)-1133) {
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env->active_tc.gpr[7] = 1; /* error flag */
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ret = -ret;
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} else {
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env->active_tc.gpr[7] = 0; /* error flag */
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}
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env->active_tc.gpr[2] = ret;
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break;
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case EXCP_CpU:
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case EXCP_RI:
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case EXCP_DSPDIS:
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force_sig(TARGET_SIGILL);
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_DEBUG:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT,
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env->active_tc.PC);
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break;
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case EXCP_FPE:
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si_code = TARGET_FPE_FLTUNK;
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if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INVALID) {
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si_code = TARGET_FPE_FLTINV;
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} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_DIV0) {
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si_code = TARGET_FPE_FLTDIV;
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} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_OVERFLOW) {
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si_code = TARGET_FPE_FLTOVF;
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} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_UNDERFLOW) {
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si_code = TARGET_FPE_FLTUND;
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} else if (GET_FP_CAUSE(env->active_fpu.fcr31) & FP_INEXACT) {
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si_code = TARGET_FPE_FLTRES;
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}
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force_sig_fault(TARGET_SIGFPE, si_code, env->active_tc.PC);
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break;
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/* The code below was inspired by the MIPS Linux kernel trap
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* handling code in arch/mips/kernel/traps.c.
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*/
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case EXCP_BREAK:
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/*
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* As described in the original Linux kernel code, the below
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* checks on 'code' are to work around an old assembly bug.
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*/
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code = env->error_code;
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if (code >= (1 << 10)) {
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code >>= 10;
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}
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do_tr_or_bp(env, code, false);
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break;
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case EXCP_TRAP:
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do_tr_or_bp(env, env->error_code, true);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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TaskState *ts = cpu->opaque;
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struct image_info *info = ts->info;
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int i;
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struct mode_req {
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bool single;
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bool soft;
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bool fr1;
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bool frdefault;
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bool fre;
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};
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static const struct mode_req fpu_reqs[] = {
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[MIPS_ABI_FP_ANY] = { true, true, true, true, true },
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[MIPS_ABI_FP_DOUBLE] = { false, false, false, true, true },
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[MIPS_ABI_FP_SINGLE] = { true, false, false, false, false },
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[MIPS_ABI_FP_SOFT] = { false, true, false, false, false },
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[MIPS_ABI_FP_OLD_64] = { false, false, false, false, false },
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[MIPS_ABI_FP_XX] = { false, false, true, true, true },
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[MIPS_ABI_FP_64] = { false, false, true, false, false },
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[MIPS_ABI_FP_64A] = { false, false, true, false, true }
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};
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/*
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* Mode requirements when .MIPS.abiflags is not present in the ELF.
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* Not present means that everything is acceptable except FR1.
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*/
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static struct mode_req none_req = { true, true, false, true, true };
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struct mode_req prog_req;
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struct mode_req interp_req;
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for(i = 0; i < 32; i++) {
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env->active_tc.gpr[i] = regs->regs[i];
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}
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env->active_tc.PC = regs->cp0_epc & ~(target_ulong)1;
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if (regs->cp0_epc & 1) {
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env->hflags |= MIPS_HFLAG_M16;
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}
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#ifdef TARGET_ABI_MIPSO32
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# define MAX_FP_ABI MIPS_ABI_FP_64A
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#else
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# define MAX_FP_ABI MIPS_ABI_FP_SOFT
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#endif
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if ((info->fp_abi > MAX_FP_ABI && info->fp_abi != MIPS_ABI_FP_UNKNOWN)
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|| (info->interp_fp_abi > MAX_FP_ABI &&
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info->interp_fp_abi != MIPS_ABI_FP_UNKNOWN)) {
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fprintf(stderr, "qemu: Unexpected FPU mode\n");
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exit(1);
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}
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prog_req = (info->fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
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: fpu_reqs[info->fp_abi];
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interp_req = (info->interp_fp_abi == MIPS_ABI_FP_UNKNOWN) ? none_req
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: fpu_reqs[info->interp_fp_abi];
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prog_req.single &= interp_req.single;
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prog_req.soft &= interp_req.soft;
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prog_req.fr1 &= interp_req.fr1;
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prog_req.frdefault &= interp_req.frdefault;
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prog_req.fre &= interp_req.fre;
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bool cpu_has_mips_r2_r6 = env->insn_flags & ISA_MIPS_R2 ||
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env->insn_flags & ISA_MIPS_R6;
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if (prog_req.fre && !prog_req.frdefault && !prog_req.fr1) {
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env->CP0_Config5 |= (1 << CP0C5_FRE);
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if (env->active_fpu.fcr0 & (1 << FCR0_FREP)) {
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env->hflags |= MIPS_HFLAG_FRE;
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}
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} else if ((prog_req.fr1 && prog_req.frdefault) ||
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(prog_req.single && !prog_req.frdefault)) {
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if ((env->active_fpu.fcr0 & (1 << FCR0_F64)
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&& cpu_has_mips_r2_r6) || prog_req.fr1) {
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env->CP0_Status |= (1 << CP0St_FR);
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env->hflags |= MIPS_HFLAG_F64;
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}
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} else if (!prog_req.fre && !prog_req.frdefault &&
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!prog_req.fr1 && !prog_req.single && !prog_req.soft) {
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fprintf(stderr, "qemu: Can't find a matching FPU mode\n");
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exit(1);
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}
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if (env->insn_flags & ISA_NANOMIPS32) {
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return;
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}
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if (((info->elf_flags & EF_MIPS_NAN2008) != 0) !=
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((env->active_fpu.fcr31 & (1 << FCR31_NAN2008)) != 0)) {
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if ((env->active_fpu.fcr31_rw_bitmask &
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(1 << FCR31_NAN2008)) == 0) {
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fprintf(stderr, "ELF binary's NaN mode not supported by CPU\n");
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exit(1);
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}
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if ((info->elf_flags & EF_MIPS_NAN2008) != 0) {
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env->active_fpu.fcr31 |= (1 << FCR31_NAN2008);
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} else {
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env->active_fpu.fcr31 &= ~(1 << FCR31_NAN2008);
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}
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restore_snan_bit_mode(env);
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}
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}
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