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130 lines
2.9 KiB
C
130 lines
2.9 KiB
C
/*
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* Infineon tc27x SoC System emulation.
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*
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* Copyright (c) 2020 Andreas Konopik <andreas.konopik@efs-auto.de>
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* Copyright (c) 2020 David Brenken <david.brenken@efs-auto.de>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef TC27X_SOC_H
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#define TC27X_SOC_H
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#include "hw/sysbus.h"
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#include "target/tricore/cpu.h"
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#include "qom/object.h"
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#define TYPE_TC27X_SOC ("tc27x-soc")
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OBJECT_DECLARE_TYPE(TC27XSoCState, TC27XSoCClass, TC27X_SOC)
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typedef struct TC27XSoCCPUMemState {
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MemoryRegion dspr;
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MemoryRegion pspr;
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MemoryRegion dcache;
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MemoryRegion dtag;
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MemoryRegion pcache;
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MemoryRegion ptag;
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} TC27XSoCCPUMemState;
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typedef struct TC27XSoCFlashMemState {
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MemoryRegion pflash0_c;
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MemoryRegion pflash1_c;
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MemoryRegion pflash0_u;
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MemoryRegion pflash1_u;
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MemoryRegion dflash0;
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MemoryRegion dflash1;
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MemoryRegion olda_c;
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MemoryRegion olda_u;
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MemoryRegion brom_c;
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MemoryRegion brom_u;
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MemoryRegion lmuram_c;
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MemoryRegion lmuram_u;
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MemoryRegion emem_c;
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MemoryRegion emem_u;
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} TC27XSoCFlashMemState;
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typedef struct TC27XSoCState {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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TriCoreCPU cpu;
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MemoryRegion dsprX;
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MemoryRegion psprX;
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TC27XSoCCPUMemState cpu0mem;
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TC27XSoCCPUMemState cpu1mem;
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TC27XSoCCPUMemState cpu2mem;
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TC27XSoCFlashMemState flashmem;
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} TC27XSoCState;
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typedef struct MemmapEntry {
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hwaddr base;
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hwaddr size;
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} MemmapEntry;
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typedef struct TC27XSoCClass {
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DeviceClass parent_class;
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const char *name;
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const char *cpu_type;
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const MemmapEntry *memmap;
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uint32_t num_cpus;
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} TC27XSoCClass;
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enum {
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TC27XD_DSPR2,
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TC27XD_DCACHE2,
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TC27XD_DTAG2,
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TC27XD_PSPR2,
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TC27XD_PCACHE2,
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TC27XD_PTAG2,
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TC27XD_DSPR1,
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TC27XD_DCACHE1,
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TC27XD_DTAG1,
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TC27XD_PSPR1,
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TC27XD_PCACHE1,
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TC27XD_PTAG1,
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TC27XD_DSPR0,
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TC27XD_PSPR0,
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TC27XD_PCACHE0,
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TC27XD_PTAG0,
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TC27XD_PFLASH0_C,
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TC27XD_PFLASH1_C,
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TC27XD_OLDA_C,
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TC27XD_BROM_C,
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TC27XD_LMURAM_C,
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TC27XD_EMEM_C,
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TC27XD_PFLASH0_U,
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TC27XD_PFLASH1_U,
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TC27XD_DFLASH0,
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TC27XD_DFLASH1,
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TC27XD_OLDA_U,
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TC27XD_BROM_U,
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TC27XD_LMURAM_U,
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TC27XD_EMEM_U,
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TC27XD_PSPRX,
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TC27XD_DSPRX,
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};
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#endif
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