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73 lines
2.1 KiB
C
73 lines
2.1 KiB
C
/*
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* ARM CMSDK APB dual-timer emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/*
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* This is a model of the "APB dual-input timer" which is part of the Cortex-M
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* System Design Kit (CMSDK) and documented in the Cortex-M System
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* Design Kit Technical Reference Manual (ARM DDI0479C):
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* https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
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*
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* QEMU interface:
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* + Clock input "TIMCLK": clock (for both timers)
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* + sysbus MMIO region 0: the register bank
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* + sysbus IRQ 0: combined timer interrupt TIMINTC
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* + sysbus IRO 1: timer block 1 interrupt TIMINT1
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* + sysbus IRQ 2: timer block 2 interrupt TIMINT2
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*/
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#ifndef CMSDK_APB_DUALTIMER_H
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#define CMSDK_APB_DUALTIMER_H
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#include "hw/sysbus.h"
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#include "hw/ptimer.h"
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#include "hw/clock.h"
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#include "qom/object.h"
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#define TYPE_CMSDK_APB_DUALTIMER "cmsdk-apb-dualtimer"
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OBJECT_DECLARE_SIMPLE_TYPE(CMSDKAPBDualTimer, CMSDK_APB_DUALTIMER)
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/* One of the two identical timer modules in the dual-timer module */
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typedef struct CMSDKAPBDualTimerModule {
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CMSDKAPBDualTimer *parent;
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struct ptimer_state *timer;
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qemu_irq timerint;
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/*
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* We must track the guest LOAD and VALUE register state by hand
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* rather than leaving this state only in the ptimer limit/count,
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* because if CONTROL.SIZE is 0 then only the low 16 bits of the
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* counter actually counts, but the high half is still guest
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* accessible.
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*/
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uint32_t load;
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uint32_t value;
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uint32_t control;
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uint32_t intstatus;
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} CMSDKAPBDualTimerModule;
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#define CMSDK_APB_DUALTIMER_NUM_MODULES 2
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struct CMSDKAPBDualTimer {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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MemoryRegion iomem;
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qemu_irq timerintc;
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Clock *timclk;
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CMSDKAPBDualTimerModule timermod[CMSDK_APB_DUALTIMER_NUM_MODULES];
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uint32_t timeritcr;
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uint32_t timeritop;
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};
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#endif
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