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211 lines
8.3 KiB
C
211 lines
8.3 KiB
C
/*
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* QEMU PowerPC XIVE2 internal structure definitions (POWER10)
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*
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* Copyright (c) 2019-2022, IBM Corporation.
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*
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* This code is licensed under the GPL version 2 or later. See the
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* COPYING file in the top-level directory.
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*/
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#ifndef PPC_XIVE2_REGS_H
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#define PPC_XIVE2_REGS_H
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/*
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* Thread Interrupt Management Area (TIMA)
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*
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* In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2
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* mode (P10), the CAM line is slightly different as the VP space was
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* increased.
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*/
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#define TM2_QW0W2_VU PPC_BIT32(0)
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#define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
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#define TM2_QW1W2_VO PPC_BIT32(0)
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#define TM2_QW1W2_HO PPC_BIT32(1)
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#define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
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#define TM2_QW2W2_VP PPC_BIT32(0)
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#define TM2_QW2W2_HP PPC_BIT32(1)
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#define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
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#define TM2_QW3W2_VT PPC_BIT32(0)
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#define TM2_QW3W2_HT PPC_BIT32(1)
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#define TM2_QW3W2_LP PPC_BIT32(6)
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#define TM2_QW3W2_LE PPC_BIT32(7)
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/*
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* Event Assignment Structure (EAS)
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*/
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typedef struct Xive2Eas {
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uint64_t w;
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#define EAS2_VALID PPC_BIT(0)
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#define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
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#define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
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#define EAS2_MASKED PPC_BIT(32) /* Masked */
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#define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
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} Xive2Eas;
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#define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
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#define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
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void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon);
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/*
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* Event Notifification Descriptor (END)
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*/
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typedef struct Xive2End {
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uint32_t w0;
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#define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
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#define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
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#define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
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#define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
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#define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
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#define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
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#define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */
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#define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */
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#define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */
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#define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */
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#define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */
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#define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */
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#define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
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#define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
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#define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
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uint32_t w1;
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#define END2_W1_ESn PPC_BITMASK32(0, 1)
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#define END2_W1_ESn_P PPC_BIT32(0)
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#define END2_W1_ESn_Q PPC_BIT32(1)
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#define END2_W1_ESe PPC_BITMASK32(2, 3)
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#define END2_W1_ESe_P PPC_BIT32(2)
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#define END2_W1_ESe_Q PPC_BIT32(3)
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#define END2_W1_GEN_FLIPPED PPC_BIT32(8)
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#define END2_W1_GENERATION PPC_BIT32(9)
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#define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
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uint32_t w2;
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#define END2_W2_RESERVED PPC_BITMASK32(4, 7)
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#define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
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uint32_t w3;
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#define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
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#define END2_W3_QSIZE PPC_BITMASK32(28, 31)
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uint32_t w4;
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#define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
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#define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
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#define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
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#define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
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uint32_t w5;
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#define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
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uint32_t w6;
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#define END2_W6_FORMAT_BIT PPC_BIT32(0)
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#define END2_W6_IGNORE PPC_BIT32(1)
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#define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
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#define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
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#define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
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uint32_t w7;
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#define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
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#define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
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#define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
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} Xive2End;
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#define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
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#define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
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#define xive2_end_is_notify(end) \
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(be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
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#define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
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#define xive2_end_is_escalate(end) \
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(be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
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#define xive2_end_is_uncond_escalation(end) \
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(be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
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#define xive2_end_is_silent_escalation(end) \
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(be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
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#define xive2_end_is_escalate_end(end) \
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(be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
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#define xive2_end_is_firmware1(end) \
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(be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
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#define xive2_end_is_firmware2(end) \
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(be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
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static inline uint64_t xive2_end_qaddr(Xive2End *end)
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{
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return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |
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(be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
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}
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void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon);
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void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
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Monitor *mon);
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void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
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Monitor *mon);
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/*
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* Notification Virtual Processor (NVP)
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*/
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typedef struct Xive2Nvp {
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uint32_t w0;
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#define NVP2_W0_VALID PPC_BIT32(0)
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#define NVP2_W0_HW PPC_BIT32(7)
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#define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
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uint32_t w1;
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#define NVP2_W1_CO PPC_BIT32(13)
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#define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
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#define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)
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#define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
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uint32_t w2;
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#define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
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#define NVP2_W2_IPB PPC_BITMASK32(8, 15)
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#define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
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uint32_t w3;
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uint32_t w4;
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#define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
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#define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
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#define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
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#define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
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uint32_t w5;
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#define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
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#define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
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#define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
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uint32_t w6;
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uint32_t w7;
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} Xive2Nvp;
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#define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
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#define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
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#define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
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/*
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* The VP number space in a block is defined by the END2_W6_VP_OFFSET
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* field of the XIVE END. When running in Gen1 mode (P9 compat mode),
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* the VP space is reduced to (1 << 19) VPs per block
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*/
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#define XIVE2_NVP_SHIFT 24
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#define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT)
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static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx)
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{
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return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx;
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}
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static inline uint32_t xive2_nvp_idx(uint32_t cam_line)
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{
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return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1);
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}
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static inline uint32_t xive2_nvp_blk(uint32_t cam_line)
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{
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return (cam_line >> XIVE2_NVP_SHIFT) & 0xf;
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}
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/*
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* Notification Virtual Group or Crowd (NVG/NVC)
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*/
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typedef struct Xive2Nvgc {
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uint32_t w0;
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#define NVGC2_W0_VALID PPC_BIT32(0)
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uint32_t w1;
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uint32_t w2;
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uint32_t w3;
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uint32_t w4;
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uint32_t w5;
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uint32_t w6;
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uint32_t w7;
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} Xive2Nvgc;
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#endif /* PPC_XIVE2_REGS_H */
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