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124 lines
3.2 KiB
C
124 lines
3.2 KiB
C
/*
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* PCIe Data Object Exchange
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*
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* Copyright (C) 2021 Avery Design Systems, Inc.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#ifndef PCIE_DOE_H
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#define PCIE_DOE_H
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#include "qemu/range.h"
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#include "qemu/typedefs.h"
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#include "hw/register.h"
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/*
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* Reference:
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* PCIe r6.0 - 7.9.24 Data Object Exchange Extended Capability
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*/
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/* Capabilities Register - r6.0 7.9.24.2 */
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#define PCI_EXP_DOE_CAP 0x04
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REG32(PCI_DOE_CAP_REG, 0)
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FIELD(PCI_DOE_CAP_REG, INTR_SUPP, 0, 1)
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FIELD(PCI_DOE_CAP_REG, DOE_INTR_MSG_NUM, 1, 11)
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/* Control Register - r6.0 7.9.24.3 */
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#define PCI_EXP_DOE_CTRL 0x08
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REG32(PCI_DOE_CAP_CONTROL, 0)
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FIELD(PCI_DOE_CAP_CONTROL, DOE_ABORT, 0, 1)
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FIELD(PCI_DOE_CAP_CONTROL, DOE_INTR_EN, 1, 1)
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FIELD(PCI_DOE_CAP_CONTROL, DOE_GO, 31, 1)
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/* Status Register - r6.0 7.9.24.4 */
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#define PCI_EXP_DOE_STATUS 0x0c
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REG32(PCI_DOE_CAP_STATUS, 0)
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FIELD(PCI_DOE_CAP_STATUS, DOE_BUSY, 0, 1)
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FIELD(PCI_DOE_CAP_STATUS, DOE_INTR_STATUS, 1, 1)
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FIELD(PCI_DOE_CAP_STATUS, DOE_ERROR, 2, 1)
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FIELD(PCI_DOE_CAP_STATUS, DATA_OBJ_RDY, 31, 1)
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/* Write Data Mailbox Register - r6.0 7.9.24.5 */
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#define PCI_EXP_DOE_WR_DATA_MBOX 0x10
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/* Read Data Mailbox Register - 7.9.xx.6 */
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#define PCI_EXP_DOE_RD_DATA_MBOX 0x14
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/* PCI-SIG defined Data Object Types - r6.0 Table 6-32 */
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#define PCI_SIG_DOE_DISCOVERY 0x00
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#define PCI_DOE_DW_SIZE_MAX (1 << 18)
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#define PCI_DOE_PROTOCOL_NUM_MAX 256
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#define DATA_OBJ_BUILD_HEADER1(v, p) (((p) << 16) | (v))
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#define DATA_OBJ_LEN_MASK(len) ((len) & (PCI_DOE_DW_SIZE_MAX - 1))
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typedef struct DOEHeader DOEHeader;
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typedef struct DOEProtocol DOEProtocol;
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typedef struct DOECap DOECap;
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struct DOEHeader {
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uint16_t vendor_id;
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uint8_t data_obj_type;
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uint8_t reserved;
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uint32_t length;
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} QEMU_PACKED;
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/* Protocol infos and rsp function callback */
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struct DOEProtocol {
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uint16_t vendor_id;
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uint8_t data_obj_type;
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bool (*handle_request)(DOECap *);
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};
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struct DOECap {
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/* Owner */
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PCIDevice *pdev;
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uint16_t offset;
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struct {
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bool intr;
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uint16_t vec;
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} cap;
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struct {
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bool abort;
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bool intr;
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bool go;
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} ctrl;
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struct {
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bool busy;
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bool intr;
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bool error;
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bool ready;
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} status;
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uint32_t *write_mbox;
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uint32_t *read_mbox;
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/* Mailbox position indicator */
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uint32_t read_mbox_idx;
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uint32_t read_mbox_len;
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uint32_t write_mbox_len;
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/* Protocols and its callback response */
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DOEProtocol *protocols;
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uint16_t protocol_num;
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};
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void pcie_doe_init(PCIDevice *pdev, DOECap *doe_cap, uint16_t offset,
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DOEProtocol *protocols, bool intr, uint16_t vec);
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void pcie_doe_fini(DOECap *doe_cap);
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bool pcie_doe_read_config(DOECap *doe_cap, uint32_t addr, int size,
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uint32_t *buf);
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void pcie_doe_write_config(DOECap *doe_cap, uint32_t addr,
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uint32_t val, int size);
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uint32_t pcie_doe_build_protocol(DOEProtocol *p);
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void *pcie_doe_get_write_mbox_ptr(DOECap *doe_cap);
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void pcie_doe_set_rsp(DOECap *doe_cap, void *rsp);
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uint32_t pcie_doe_get_obj_len(void *obj);
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#endif /* PCIE_DOE_H */
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