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Jonathan Cameron 7bd1900b36 pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup. ... As the CXLState will no long be accessible via MachineState at time of PXB_CXL realization, come back later from the machine specific code to fill in the missing memory region setup. Only at this stage is it possible to check if cxl=on, so that check is moved to this later point. Note that for multiple host bridges, the allocation order of the register spaces is changed. This will be reflected in ACPI CEDT. Stubs are added to handle case of CONFIG_PXB=n for machines that call these functions. The bus walking logic is common to all machines so add a utility function + stub to cxl-host*. Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Ben Widawsky <ben@bwidawsk.net> Message-Id: <20220608145440.26106-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2 years ago
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pci_expander_bridge.h	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2 years ago
simba.h	Use OBJECT_DECLARE_SIMPLE_TYPE when possible	4 years ago
xio3130_downstream.h	pci: expose TYPE_XIO3130_DOWNSTREAM name	3 years ago