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1b2b12376c
This patch introduce ECAP_PASID via "x-pasid-mode". Based on the existing support for scalable mode, we need to implement the following missing parts: 1) tag VTDAddressSpace with PASID and support IOMMU/DMA translation with PASID 2) tag IOTLB with PASID 3) PASID cache and its flush 4) PASID based IOTLB invalidation For simplicity PASID cache is not implemented so we can simply implement the PASID cache flush as a no and leave it to be implemented in the future. For PASID based IOTLB invalidation, since we haven't had L1 stage support, the PASID based IOTLB invalidation is not implemented yet. For PASID based device IOTLB invalidation, it requires the support for vhost so we forbid enabling device IOTLB when PASID is enabled now. Those work could be done in the future. Note that though PASID based IOMMU translation is ready but no device can issue PASID DMA right now. In this case, PCI_NO_PASID is used as PASID to identify the address without PASID. vtd_find_add_as() has been extended to provision address space with PASID which could be utilized by the future extension of PCI core to allow device model to use PASID based DMA translation. This feature would be useful for: 1) prototyping PASID support for devices like virtio 2) future vPASID work 3) future PRS and vSVA work Reviewed-by: Peter Xu <peterx@redhat.com> Signed-off-by: Jason Wang <jasowang@redhat.com> Message-Id: <20221028061436.30093-5-jasowang@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com> |
2 years ago | |
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| .. | ||
| apic-msidef.h | 7 years ago | |
| apic.h | 6 years ago | |
| apic_internal.h | 4 years ago | |
| hostmem-epc.h | 3 years ago | |
| ich9.h | 4 years ago | |
| intel_iommu.h | 2 years ago | |
| ioapic.h | 4 years ago | |
| ioapic_internal.h | 3 years ago | |
| microvm.h | 3 years ago | |
| pc.h | 2 years ago | |
| sgx-epc.h | 3 years ago | |
| topology.h | 4 years ago | |
| vmport.h | 4 years ago | |
| x86-iommu.h | 3 years ago | |
| x86.h | 2 years ago | |