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165 lines
4.4 KiB
C
165 lines
4.4 KiB
C
/*
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* QEMU USB OHCI Emulation
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* Copyright (c) 2004 Gianni Tedesco
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* Copyright (c) 2006 CodeSourcery
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* Copyright (c) 2006 Openedhand Ltd.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/timer.h"
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#include "hw/usb.h"
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#include "migration/vmstate.h"
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#include "hw/pci/pci.h"
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#include "hw/sysbus.h"
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#include "hw/qdev-dma.h"
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#include "hw/qdev-properties.h"
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#include "trace.h"
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#include "hcd-ohci.h"
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#include "qom/object.h"
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#define TYPE_PCI_OHCI "pci-ohci"
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OBJECT_DECLARE_SIMPLE_TYPE(OHCIPCIState, PCI_OHCI)
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struct OHCIPCIState {
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/*< private >*/
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PCIDevice parent_obj;
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/*< public >*/
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OHCIState state;
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char *masterbus;
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uint32_t num_ports;
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uint32_t firstport;
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};
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/**
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* A typical PCI OHCI will additionally set PERR in its configspace to
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* signal that it got an error.
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*/
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static void ohci_pci_die(struct OHCIState *ohci)
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{
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OHCIPCIState *dev = container_of(ohci, OHCIPCIState, state);
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ohci_sysbus_die(ohci);
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pci_set_word(dev->parent_obj.config + PCI_STATUS,
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PCI_STATUS_DETECTED_PARITY);
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}
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static void usb_ohci_realize_pci(PCIDevice *dev, Error **errp)
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{
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Error *err = NULL;
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OHCIPCIState *ohci = PCI_OHCI(dev);
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dev->config[PCI_CLASS_PROG] = 0x10; /* OHCI */
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dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin A */
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usb_ohci_init(&ohci->state, DEVICE(dev), ohci->num_ports, 0,
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ohci->masterbus, ohci->firstport,
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pci_get_address_space(dev), ohci_pci_die, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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ohci->state.irq = pci_allocate_irq(dev);
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pci_register_bar(dev, 0, 0, &ohci->state.mem);
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}
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static void usb_ohci_exit(PCIDevice *dev)
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{
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OHCIPCIState *ohci = PCI_OHCI(dev);
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OHCIState *s = &ohci->state;
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trace_usb_ohci_exit(s->name);
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ohci_bus_stop(s);
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if (s->async_td) {
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usb_cancel_packet(&s->usb_packet);
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s->async_td = 0;
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}
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ohci_stop_endpoints(s);
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if (!ohci->masterbus) {
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usb_bus_release(&s->bus);
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}
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timer_free(s->eof_timer);
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}
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static void usb_ohci_reset_pci(DeviceState *d)
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{
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PCIDevice *dev = PCI_DEVICE(d);
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OHCIPCIState *ohci = PCI_OHCI(dev);
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OHCIState *s = &ohci->state;
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ohci_hard_reset(s);
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}
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static Property ohci_pci_properties[] = {
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DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus),
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DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3),
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DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_ohci = {
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.name = "ohci",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_PCI_DEVICE(parent_obj, OHCIPCIState),
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VMSTATE_STRUCT(state, OHCIPCIState, 1, vmstate_ohci_state, OHCIState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void ohci_pci_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->realize = usb_ohci_realize_pci;
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k->exit = usb_ohci_exit;
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k->vendor_id = PCI_VENDOR_ID_APPLE;
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k->device_id = PCI_DEVICE_ID_APPLE_IPID_USB;
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k->class_id = PCI_CLASS_SERIAL_USB;
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set_bit(DEVICE_CATEGORY_USB, dc->categories);
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dc->desc = "Apple USB Controller";
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device_class_set_props(dc, ohci_pci_properties);
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dc->hotpluggable = false;
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dc->vmsd = &vmstate_ohci;
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dc->reset = usb_ohci_reset_pci;
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}
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static const TypeInfo ohci_pci_info = {
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.name = TYPE_PCI_OHCI,
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(OHCIPCIState),
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.class_init = ohci_pci_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
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{ },
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},
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};
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static void ohci_pci_register_types(void)
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{
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type_register_static(&ohci_pci_info);
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}
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type_init(ohci_pci_register_types)
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