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647 lines
22 KiB
C
647 lines
22 KiB
C
/*
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* QEMU model of the Ibex SPI Controller
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* SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/
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*
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* Copyright (C) 2022 Western Digital
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qemu/module.h"
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#include "hw/ssi/ibex_spi_host.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "migration/vmstate.h"
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#include "trace.h"
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REG32(INTR_STATE, 0x00)
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FIELD(INTR_STATE, ERROR, 0, 1)
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FIELD(INTR_STATE, SPI_EVENT, 1, 1)
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REG32(INTR_ENABLE, 0x04)
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FIELD(INTR_ENABLE, ERROR, 0, 1)
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FIELD(INTR_ENABLE, SPI_EVENT, 1, 1)
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REG32(INTR_TEST, 0x08)
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FIELD(INTR_TEST, ERROR, 0, 1)
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FIELD(INTR_TEST, SPI_EVENT, 1, 1)
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REG32(ALERT_TEST, 0x0c)
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FIELD(ALERT_TEST, FETAL_TEST, 0, 1)
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REG32(CONTROL, 0x10)
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FIELD(CONTROL, RX_WATERMARK, 0, 8)
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FIELD(CONTROL, TX_WATERMARK, 1, 8)
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FIELD(CONTROL, OUTPUT_EN, 29, 1)
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FIELD(CONTROL, SW_RST, 30, 1)
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FIELD(CONTROL, SPIEN, 31, 1)
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REG32(STATUS, 0x14)
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FIELD(STATUS, TXQD, 0, 8)
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FIELD(STATUS, RXQD, 18, 8)
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FIELD(STATUS, CMDQD, 16, 3)
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FIELD(STATUS, RXWM, 20, 1)
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FIELD(STATUS, BYTEORDER, 22, 1)
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FIELD(STATUS, RXSTALL, 23, 1)
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FIELD(STATUS, RXEMPTY, 24, 1)
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FIELD(STATUS, RXFULL, 25, 1)
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FIELD(STATUS, TXWM, 26, 1)
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FIELD(STATUS, TXSTALL, 27, 1)
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FIELD(STATUS, TXEMPTY, 28, 1)
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FIELD(STATUS, TXFULL, 29, 1)
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FIELD(STATUS, ACTIVE, 30, 1)
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FIELD(STATUS, READY, 31, 1)
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REG32(CONFIGOPTS, 0x18)
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FIELD(CONFIGOPTS, CLKDIV_0, 0, 16)
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FIELD(CONFIGOPTS, CSNIDLE_0, 16, 4)
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FIELD(CONFIGOPTS, CSNTRAIL_0, 20, 4)
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FIELD(CONFIGOPTS, CSNLEAD_0, 24, 4)
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FIELD(CONFIGOPTS, FULLCYC_0, 29, 1)
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FIELD(CONFIGOPTS, CPHA_0, 30, 1)
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FIELD(CONFIGOPTS, CPOL_0, 31, 1)
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REG32(CSID, 0x1c)
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FIELD(CSID, CSID, 0, 32)
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REG32(COMMAND, 0x20)
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FIELD(COMMAND, LEN, 0, 8)
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FIELD(COMMAND, CSAAT, 9, 1)
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FIELD(COMMAND, SPEED, 10, 2)
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FIELD(COMMAND, DIRECTION, 12, 2)
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REG32(ERROR_ENABLE, 0x2c)
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FIELD(ERROR_ENABLE, CMDBUSY, 0, 1)
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FIELD(ERROR_ENABLE, OVERFLOW, 1, 1)
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FIELD(ERROR_ENABLE, UNDERFLOW, 2, 1)
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FIELD(ERROR_ENABLE, CMDINVAL, 3, 1)
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FIELD(ERROR_ENABLE, CSIDINVAL, 4, 1)
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REG32(ERROR_STATUS, 0x30)
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FIELD(ERROR_STATUS, CMDBUSY, 0, 1)
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FIELD(ERROR_STATUS, OVERFLOW, 1, 1)
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FIELD(ERROR_STATUS, UNDERFLOW, 2, 1)
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FIELD(ERROR_STATUS, CMDINVAL, 3, 1)
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FIELD(ERROR_STATUS, CSIDINVAL, 4, 1)
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FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1)
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REG32(EVENT_ENABLE, 0x34)
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FIELD(EVENT_ENABLE, RXFULL, 0, 1)
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FIELD(EVENT_ENABLE, TXEMPTY, 1, 1)
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FIELD(EVENT_ENABLE, RXWM, 2, 1)
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FIELD(EVENT_ENABLE, TXWM, 3, 1)
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FIELD(EVENT_ENABLE, READY, 4, 1)
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FIELD(EVENT_ENABLE, IDLE, 5, 1)
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static inline uint8_t div4_round_up(uint8_t dividend)
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{
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return (dividend + 3) / 4;
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}
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static void ibex_spi_rxfifo_reset(IbexSPIHostState *s)
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{
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uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
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/* Empty the RX FIFO and assert RXEMPTY */
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fifo8_reset(&s->rx_fifo);
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data = FIELD_DP32(data, STATUS, RXFULL, 0);
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data = FIELD_DP32(data, STATUS, RXEMPTY, 1);
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s->regs[IBEX_SPI_HOST_STATUS] = data;
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}
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static void ibex_spi_txfifo_reset(IbexSPIHostState *s)
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{
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uint32_t data = s->regs[IBEX_SPI_HOST_STATUS];
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/* Empty the TX FIFO and assert TXEMPTY */
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fifo8_reset(&s->tx_fifo);
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data = FIELD_DP32(data, STATUS, TXFULL, 0);
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data = FIELD_DP32(data, STATUS, TXEMPTY, 1);
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s->regs[IBEX_SPI_HOST_STATUS] = data;
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}
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static void ibex_spi_host_reset(DeviceState *dev)
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{
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IbexSPIHostState *s = IBEX_SPI_HOST(dev);
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trace_ibex_spi_host_reset("Resetting Ibex SPI");
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/* SPI Host Register Reset */
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s->regs[IBEX_SPI_HOST_INTR_STATE] = 0x00;
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s->regs[IBEX_SPI_HOST_INTR_ENABLE] = 0x00;
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s->regs[IBEX_SPI_HOST_INTR_TEST] = 0x00;
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s->regs[IBEX_SPI_HOST_ALERT_TEST] = 0x00;
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s->regs[IBEX_SPI_HOST_CONTROL] = 0x7f;
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s->regs[IBEX_SPI_HOST_STATUS] = 0x00;
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s->regs[IBEX_SPI_HOST_CONFIGOPTS] = 0x00;
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s->regs[IBEX_SPI_HOST_CSID] = 0x00;
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s->regs[IBEX_SPI_HOST_COMMAND] = 0x00;
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/* RX/TX Modelled by FIFO */
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s->regs[IBEX_SPI_HOST_RXDATA] = 0x00;
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s->regs[IBEX_SPI_HOST_TXDATA] = 0x00;
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s->regs[IBEX_SPI_HOST_ERROR_ENABLE] = 0x1F;
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s->regs[IBEX_SPI_HOST_ERROR_STATUS] = 0x00;
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s->regs[IBEX_SPI_HOST_EVENT_ENABLE] = 0x00;
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ibex_spi_rxfifo_reset(s);
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ibex_spi_txfifo_reset(s);
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s->init_status = true;
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return;
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}
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/*
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* Check if we need to trigger an interrupt.
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* The two interrupts lines (host_err and event) can
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* be enabled separately in 'IBEX_SPI_HOST_INTR_ENABLE'.
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*
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* Interrupts are triggered based on the ones
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* enabled in the `IBEX_SPI_HOST_EVENT_ENABLE` and `IBEX_SPI_HOST_ERROR_ENABLE`.
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*/
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static void ibex_spi_host_irq(IbexSPIHostState *s)
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{
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uint32_t intr_test_reg = s->regs[IBEX_SPI_HOST_INTR_TEST];
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uint32_t intr_en_reg = s->regs[IBEX_SPI_HOST_INTR_ENABLE];
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uint32_t intr_state_reg = s->regs[IBEX_SPI_HOST_INTR_STATE];
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uint32_t err_en_reg = s->regs[IBEX_SPI_HOST_ERROR_ENABLE];
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uint32_t event_en_reg = s->regs[IBEX_SPI_HOST_EVENT_ENABLE];
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uint32_t err_status_reg = s->regs[IBEX_SPI_HOST_ERROR_STATUS];
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uint32_t status_reg = s->regs[IBEX_SPI_HOST_STATUS];
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bool error_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, ERROR);
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bool event_en = FIELD_EX32(intr_en_reg, INTR_ENABLE, SPI_EVENT);
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bool err_pending = FIELD_EX32(intr_state_reg, INTR_STATE, ERROR);
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bool status_pending = FIELD_EX32(intr_state_reg, INTR_STATE, SPI_EVENT);
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int err_irq = 0, event_irq = 0;
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/* Error IRQ enabled and Error IRQ Cleared */
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if (error_en && !err_pending) {
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/* Event enabled, Interrupt Test Error */
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if (FIELD_EX32(intr_test_reg, INTR_TEST, ERROR)) {
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err_irq = 1;
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} else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDBUSY) &&
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FIELD_EX32(err_status_reg, ERROR_STATUS, CMDBUSY)) {
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/* Wrote to COMMAND when not READY */
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err_irq = 1;
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} else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CMDINVAL) &&
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FIELD_EX32(err_status_reg, ERROR_STATUS, CMDINVAL)) {
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/* Invalid command segment */
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err_irq = 1;
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} else if (FIELD_EX32(err_en_reg, ERROR_ENABLE, CSIDINVAL) &&
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FIELD_EX32(err_status_reg, ERROR_STATUS, CSIDINVAL)) {
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/* Invalid value for CSID */
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err_irq = 1;
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}
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if (err_irq) {
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s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_ERROR_MASK;
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}
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qemu_set_irq(s->host_err, err_irq);
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}
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/* Event IRQ Enabled and Event IRQ Cleared */
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if (event_en && !status_pending) {
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if (FIELD_EX32(intr_test_reg, INTR_STATE, SPI_EVENT)) {
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/* Event enabled, Interrupt Test Event */
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event_irq = 1;
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} else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, READY) &&
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FIELD_EX32(status_reg, STATUS, READY)) {
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/* SPI Host ready for next command */
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event_irq = 1;
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} else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, TXEMPTY) &&
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FIELD_EX32(status_reg, STATUS, TXEMPTY)) {
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/* SPI TXEMPTY, TXFIFO drained */
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event_irq = 1;
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} else if (FIELD_EX32(event_en_reg, EVENT_ENABLE, RXFULL) &&
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FIELD_EX32(status_reg, STATUS, RXFULL)) {
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/* SPI RXFULL, RXFIFO full */
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event_irq = 1;
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}
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if (event_irq) {
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s->regs[IBEX_SPI_HOST_INTR_STATE] |= R_INTR_STATE_SPI_EVENT_MASK;
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}
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qemu_set_irq(s->event, event_irq);
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}
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}
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static void ibex_spi_host_transfer(IbexSPIHostState *s)
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{
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uint32_t rx, tx, data;
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/* Get num of one byte transfers */
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uint8_t segment_len = FIELD_EX32(s->regs[IBEX_SPI_HOST_COMMAND],
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COMMAND, LEN);
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while (segment_len > 0) {
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if (fifo8_is_empty(&s->tx_fifo)) {
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/* Assert Stall */
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s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXSTALL_MASK;
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break;
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} else if (fifo8_is_full(&s->rx_fifo)) {
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/* Assert Stall */
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s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXSTALL_MASK;
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break;
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} else {
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tx = fifo8_pop(&s->tx_fifo);
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}
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rx = ssi_transfer(s->ssi, tx);
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trace_ibex_spi_host_transfer(tx, rx);
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if (!fifo8_is_full(&s->rx_fifo)) {
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fifo8_push(&s->rx_fifo, rx);
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} else {
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/* Assert RXFULL */
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s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXFULL_MASK;
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}
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--segment_len;
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}
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data = s->regs[IBEX_SPI_HOST_STATUS];
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/* Assert Ready */
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data = FIELD_DP32(data, STATUS, READY, 1);
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/* Set RXQD */
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data = FIELD_DP32(data, STATUS, RXQD, div4_round_up(segment_len));
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/* Set TXQD */
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data = FIELD_DP32(data, STATUS, TXQD, fifo8_num_used(&s->tx_fifo) / 4);
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/* Clear TXFULL */
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data = FIELD_DP32(data, STATUS, TXFULL, 0);
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/* Reset RXEMPTY */
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data = FIELD_DP32(data, STATUS, RXEMPTY, 0);
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/* Update register status */
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s->regs[IBEX_SPI_HOST_STATUS] = data;
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/* Drop remaining bytes that exceed segment_len */
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ibex_spi_txfifo_reset(s);
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ibex_spi_host_irq(s);
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}
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static uint64_t ibex_spi_host_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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IbexSPIHostState *s = opaque;
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uint32_t rc = 0;
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uint8_t rx_byte = 0;
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trace_ibex_spi_host_read(addr, size);
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/* Match reg index */
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addr = addr >> 2;
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switch (addr) {
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/* Skipping any W/O registers */
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case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE:
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case IBEX_SPI_HOST_CONTROL...IBEX_SPI_HOST_STATUS:
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rc = s->regs[addr];
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break;
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case IBEX_SPI_HOST_CSID:
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rc = s->regs[addr];
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break;
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case IBEX_SPI_HOST_CONFIGOPTS:
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rc = s->config_opts[s->regs[IBEX_SPI_HOST_CSID]];
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break;
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case IBEX_SPI_HOST_TXDATA:
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rc = s->regs[addr];
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break;
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case IBEX_SPI_HOST_RXDATA:
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/* Clear RXFULL */
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s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_RXFULL_MASK;
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for (int i = 0; i < 4; ++i) {
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if (fifo8_is_empty(&s->rx_fifo)) {
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/* Assert RXEMPTY, no IRQ */
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s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_RXEMPTY_MASK;
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s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
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R_ERROR_STATUS_UNDERFLOW_MASK;
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return rc;
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}
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rx_byte = fifo8_pop(&s->rx_fifo);
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rc |= rx_byte << (i * 8);
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}
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break;
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case IBEX_SPI_HOST_ERROR_ENABLE...IBEX_SPI_HOST_EVENT_ENABLE:
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rc = s->regs[addr];
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n",
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addr << 2);
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}
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return rc;
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}
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static void ibex_spi_host_write(void *opaque, hwaddr addr,
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uint64_t val64, unsigned int size)
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{
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IbexSPIHostState *s = opaque;
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uint32_t val32 = val64;
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uint32_t shift_mask = 0xff, status = 0, data = 0;
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uint8_t txqd_len;
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trace_ibex_spi_host_write(addr, size, val64);
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/* Match reg index */
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addr = addr >> 2;
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switch (addr) {
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/* Skipping any R/O registers */
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case IBEX_SPI_HOST_INTR_STATE:
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/* rw1c status register */
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if (FIELD_EX32(val32, INTR_STATE, ERROR)) {
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data = FIELD_DP32(data, INTR_STATE, ERROR, 0);
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}
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if (FIELD_EX32(val32, INTR_STATE, SPI_EVENT)) {
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data = FIELD_DP32(data, INTR_STATE, SPI_EVENT, 0);
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}
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s->regs[addr] = data;
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break;
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case IBEX_SPI_HOST_INTR_ENABLE:
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s->regs[addr] = val32;
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break;
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case IBEX_SPI_HOST_INTR_TEST:
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s->regs[addr] = val32;
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ibex_spi_host_irq(s);
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break;
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case IBEX_SPI_HOST_ALERT_TEST:
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s->regs[addr] = val32;
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qemu_log_mask(LOG_UNIMP,
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"%s: SPI_ALERT_TEST is not supported\n", __func__);
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break;
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case IBEX_SPI_HOST_CONTROL:
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s->regs[addr] = val32;
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if (val32 & R_CONTROL_SW_RST_MASK) {
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ibex_spi_host_reset((DeviceState *)s);
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/* Clear active if any */
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s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_ACTIVE_MASK;
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}
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if (val32 & R_CONTROL_OUTPUT_EN_MASK) {
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qemu_log_mask(LOG_UNIMP,
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"%s: CONTROL_OUTPUT_EN is not supported\n", __func__);
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}
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break;
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case IBEX_SPI_HOST_CONFIGOPTS:
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/* Update the respective config-opts register based on CSIDth index */
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s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] = val32;
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qemu_log_mask(LOG_UNIMP,
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"%s: CONFIGOPTS Hardware settings not supported\n",
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__func__);
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break;
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case IBEX_SPI_HOST_CSID:
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if (val32 >= s->num_cs) {
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/* CSID exceeds max num_cs */
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s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
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R_ERROR_STATUS_CSIDINVAL_MASK;
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ibex_spi_host_irq(s);
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return;
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}
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s->regs[addr] = val32;
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break;
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case IBEX_SPI_HOST_COMMAND:
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s->regs[addr] = val32;
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/* STALL, IP not enabled */
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if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_CONTROL],
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CONTROL, SPIEN))) {
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return;
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}
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/* SPI not ready, IRQ Error */
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if (!(FIELD_EX32(s->regs[IBEX_SPI_HOST_STATUS],
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STATUS, READY))) {
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s->regs[IBEX_SPI_HOST_ERROR_STATUS] |= R_ERROR_STATUS_CMDBUSY_MASK;
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ibex_spi_host_irq(s);
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return;
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}
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/* Assert Not Ready */
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s->regs[IBEX_SPI_HOST_STATUS] &= ~R_STATUS_READY_MASK;
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if (FIELD_EX32(val32, COMMAND, DIRECTION) != BIDIRECTIONAL_TRANSFER) {
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qemu_log_mask(LOG_UNIMP,
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"%s: Rx Only/Tx Only are not supported\n", __func__);
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}
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if (val32 & R_COMMAND_CSAAT_MASK) {
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qemu_log_mask(LOG_UNIMP,
|
|
"%s: CSAAT is not supported\n", __func__);
|
|
}
|
|
if (val32 & R_COMMAND_SPEED_MASK) {
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: SPEED is not supported\n", __func__);
|
|
}
|
|
|
|
/* Set Transfer Callback */
|
|
timer_mod(s->fifo_trigger_handle,
|
|
qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
|
|
(TX_INTERRUPT_TRIGGER_DELAY_NS));
|
|
|
|
break;
|
|
case IBEX_SPI_HOST_TXDATA:
|
|
/*
|
|
* This is a hardware `feature` where
|
|
* the first word written to TXDATA after init is omitted entirely
|
|
*/
|
|
if (s->init_status) {
|
|
s->init_status = false;
|
|
return;
|
|
}
|
|
|
|
for (int i = 0; i < 4; ++i) {
|
|
/* Attempting to write when TXFULL */
|
|
if (fifo8_is_full(&s->tx_fifo)) {
|
|
/* Assert RXEMPTY, no IRQ */
|
|
s->regs[IBEX_SPI_HOST_STATUS] |= R_STATUS_TXFULL_MASK;
|
|
s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=
|
|
R_ERROR_STATUS_OVERFLOW_MASK;
|
|
ibex_spi_host_irq(s);
|
|
return;
|
|
}
|
|
/* Byte ordering is set by the IP */
|
|
status = s->regs[IBEX_SPI_HOST_STATUS];
|
|
if (FIELD_EX32(status, STATUS, BYTEORDER) == 0) {
|
|
/* LE: LSB transmitted first (default for ibex processor) */
|
|
shift_mask = 0xff << (i * 8);
|
|
} else {
|
|
/* BE: MSB transmitted first */
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: Big endian is not supported\n", __func__);
|
|
}
|
|
|
|
fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8));
|
|
}
|
|
status = s->regs[IBEX_SPI_HOST_STATUS];
|
|
/* Reset TXEMPTY */
|
|
status = FIELD_DP32(status, STATUS, TXEMPTY, 0);
|
|
/* Update TXQD */
|
|
txqd_len = FIELD_EX32(status, STATUS, TXQD);
|
|
/* Partial bytes (size < 4) are padded, in words. */
|
|
txqd_len += 1;
|
|
status = FIELD_DP32(status, STATUS, TXQD, txqd_len);
|
|
/* Assert Ready */
|
|
status = FIELD_DP32(status, STATUS, READY, 1);
|
|
/* Update register status */
|
|
s->regs[IBEX_SPI_HOST_STATUS] = status;
|
|
break;
|
|
case IBEX_SPI_HOST_ERROR_ENABLE:
|
|
s->regs[addr] = val32;
|
|
|
|
if (val32 & R_ERROR_ENABLE_CMDINVAL_MASK) {
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: Segment Length is not supported\n", __func__);
|
|
}
|
|
break;
|
|
case IBEX_SPI_HOST_ERROR_STATUS:
|
|
/*
|
|
* Indicates any errors that have occurred.
|
|
* When an error occurs, the corresponding bit must be cleared
|
|
* here before issuing any further commands
|
|
*/
|
|
status = s->regs[addr];
|
|
/* rw1c status register */
|
|
if (FIELD_EX32(val32, ERROR_STATUS, CMDBUSY)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, CMDBUSY, 0);
|
|
}
|
|
if (FIELD_EX32(val32, ERROR_STATUS, OVERFLOW)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, OVERFLOW, 0);
|
|
}
|
|
if (FIELD_EX32(val32, ERROR_STATUS, UNDERFLOW)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, UNDERFLOW, 0);
|
|
}
|
|
if (FIELD_EX32(val32, ERROR_STATUS, CMDINVAL)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, CMDINVAL, 0);
|
|
}
|
|
if (FIELD_EX32(val32, ERROR_STATUS, CSIDINVAL)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, CSIDINVAL, 0);
|
|
}
|
|
if (FIELD_EX32(val32, ERROR_STATUS, ACCESSINVAL)) {
|
|
status = FIELD_DP32(status, ERROR_STATUS, ACCESSINVAL, 0);
|
|
}
|
|
s->regs[addr] = status;
|
|
break;
|
|
case IBEX_SPI_HOST_EVENT_ENABLE:
|
|
/* Controls which classes of SPI events raise an interrupt. */
|
|
s->regs[addr] = val32;
|
|
|
|
if (val32 & R_EVENT_ENABLE_RXWM_MASK) {
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: RXWM is not supported\n", __func__);
|
|
}
|
|
if (val32 & R_EVENT_ENABLE_TXWM_MASK) {
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: TXWM is not supported\n", __func__);
|
|
}
|
|
|
|
if (val32 & R_EVENT_ENABLE_IDLE_MASK) {
|
|
qemu_log_mask(LOG_UNIMP,
|
|
"%s: IDLE is not supported\n", __func__);
|
|
}
|
|
break;
|
|
default:
|
|
qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n",
|
|
addr << 2);
|
|
}
|
|
}
|
|
|
|
static const MemoryRegionOps ibex_spi_ops = {
|
|
.read = ibex_spi_host_read,
|
|
.write = ibex_spi_host_write,
|
|
/* Ibex default LE */
|
|
.endianness = DEVICE_LITTLE_ENDIAN,
|
|
};
|
|
|
|
static Property ibex_spi_properties[] = {
|
|
DEFINE_PROP_UINT32("num_cs", IbexSPIHostState, num_cs, 1),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static const VMStateDescription vmstate_ibex = {
|
|
.name = TYPE_IBEX_SPI_HOST,
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32_ARRAY(regs, IbexSPIHostState, IBEX_SPI_HOST_MAX_REGS),
|
|
VMSTATE_VARRAY_UINT32(config_opts, IbexSPIHostState,
|
|
num_cs, 0, vmstate_info_uint32, uint32_t),
|
|
VMSTATE_FIFO8(rx_fifo, IbexSPIHostState),
|
|
VMSTATE_FIFO8(tx_fifo, IbexSPIHostState),
|
|
VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexSPIHostState),
|
|
VMSTATE_BOOL(init_status, IbexSPIHostState),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static void fifo_trigger_update(void *opaque)
|
|
{
|
|
IbexSPIHostState *s = opaque;
|
|
ibex_spi_host_transfer(s);
|
|
}
|
|
|
|
static void ibex_spi_host_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
IbexSPIHostState *s = IBEX_SPI_HOST(dev);
|
|
int i;
|
|
|
|
s->ssi = ssi_create_bus(dev, "ssi");
|
|
s->cs_lines = g_new0(qemu_irq, s->num_cs);
|
|
|
|
for (i = 0; i < s->num_cs; ++i) {
|
|
sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]);
|
|
}
|
|
|
|
/* Setup CONFIGOPTS Multi-register */
|
|
s->config_opts = g_new0(uint32_t, s->num_cs);
|
|
|
|
/* Setup FIFO Interrupt Timer */
|
|
s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
|
fifo_trigger_update, s);
|
|
|
|
/* FIFO sizes as per OT Spec */
|
|
fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN);
|
|
fifo8_create(&s->rx_fifo, IBEX_SPI_HOST_RXFIFO_LEN);
|
|
}
|
|
|
|
static void ibex_spi_host_init(Object *obj)
|
|
{
|
|
IbexSPIHostState *s = IBEX_SPI_HOST(obj);
|
|
|
|
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->host_err);
|
|
sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->event);
|
|
|
|
memory_region_init_io(&s->mmio, obj, &ibex_spi_ops, s,
|
|
TYPE_IBEX_SPI_HOST, 0x1000);
|
|
sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio);
|
|
}
|
|
|
|
static void ibex_spi_host_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
dc->realize = ibex_spi_host_realize;
|
|
dc->reset = ibex_spi_host_reset;
|
|
dc->vmsd = &vmstate_ibex;
|
|
device_class_set_props(dc, ibex_spi_properties);
|
|
}
|
|
|
|
static const TypeInfo ibex_spi_host_info = {
|
|
.name = TYPE_IBEX_SPI_HOST,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(IbexSPIHostState),
|
|
.instance_init = ibex_spi_host_init,
|
|
.class_init = ibex_spi_host_class_init,
|
|
};
|
|
|
|
static void ibex_spi_host_register_types(void)
|
|
{
|
|
type_register_static(&ibex_spi_host_info);
|
|
}
|
|
|
|
type_init(ibex_spi_host_register_types)
|