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758 lines
22 KiB
C
758 lines
22 KiB
C
/*
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* QEMU PowerPC 4xx embedded processors SDRAM controller emulation
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*
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* DDR SDRAM controller:
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* Copyright (c) 2007 Jocelyn Mayer
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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* DDR2 SDRAM controller:
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* Copyright (c) 2012 François Revol
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* Copyright (c) 2016-2019 BALATON Zoltan
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*
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* This work is licensed under the GNU GPL license version 2 or later.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h" /* get_system_memory() */
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/ppc/ppc4xx.h"
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#include "trace.h"
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/*****************************************************************************/
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/* Shared functions */
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/*
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* Split RAM between SDRAM banks.
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*
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* sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1]
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* and must be 0-terminated.
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*
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* The 4xx SDRAM controller supports a small number of banks, and each bank
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* must be one of a small set of sizes. The number of banks and the supported
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* sizes varies by SoC.
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*/
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static bool ppc4xx_sdram_banks(MemoryRegion *ram, int nr_banks,
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Ppc4xxSdramBank ram_banks[],
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const ram_addr_t sdram_bank_sizes[],
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Error **errp)
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{
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ERRP_GUARD();
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ram_addr_t size_left = memory_region_size(ram);
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ram_addr_t base = 0;
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ram_addr_t bank_size;
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int i;
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int j;
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for (i = 0; i < nr_banks; i++) {
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for (j = 0; sdram_bank_sizes[j] != 0; j++) {
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bank_size = sdram_bank_sizes[j];
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if (bank_size <= size_left) {
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char name[32];
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ram_banks[i].base = base;
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ram_banks[i].size = bank_size;
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base += bank_size;
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size_left -= bank_size;
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snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
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memory_region_init_alias(&ram_banks[i].ram, NULL, name, ram,
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ram_banks[i].base, ram_banks[i].size);
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break;
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}
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}
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if (!size_left) {
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/* No need to use the remaining banks. */
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break;
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}
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}
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if (size_left) {
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ram_addr_t used_size = memory_region_size(ram) - size_left;
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GString *s = g_string_new(NULL);
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for (i = 0; sdram_bank_sizes[i]; i++) {
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g_string_append_printf(s, "%" PRIi64 "%s",
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sdram_bank_sizes[i] / MiB,
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sdram_bank_sizes[i + 1] ? ", " : "");
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}
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error_setg(errp, "Invalid SDRAM banks");
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error_append_hint(errp, "at most %d bank%s of %s MiB each supported\n",
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nr_banks, nr_banks == 1 ? "" : "s", s->str);
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error_append_hint(errp, "Possible valid RAM size: %" PRIi64 " MiB\n",
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used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB);
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g_string_free(s, true);
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return false;
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}
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return true;
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}
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static void sdram_bank_map(Ppc4xxSdramBank *bank)
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{
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trace_ppc4xx_sdram_map(bank->base, bank->size);
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memory_region_init(&bank->container, NULL, "sdram-container", bank->size);
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memory_region_add_subregion(&bank->container, 0, &bank->ram);
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memory_region_add_subregion(get_system_memory(), bank->base,
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&bank->container);
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}
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static void sdram_bank_unmap(Ppc4xxSdramBank *bank)
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{
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trace_ppc4xx_sdram_unmap(bank->base, bank->size);
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memory_region_del_subregion(get_system_memory(), &bank->container);
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memory_region_del_subregion(&bank->container, &bank->ram);
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object_unparent(OBJECT(&bank->container));
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}
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static void sdram_bank_set_bcr(Ppc4xxSdramBank *bank, uint32_t bcr,
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hwaddr base, hwaddr size, int enabled)
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{
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if (memory_region_is_mapped(&bank->container)) {
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sdram_bank_unmap(bank);
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}
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bank->bcr = bcr;
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bank->base = base;
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bank->size = size;
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if (enabled && (bcr & 1)) {
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sdram_bank_map(bank);
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}
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}
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enum {
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SDRAM0_CFGADDR = 0x010,
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SDRAM0_CFGDATA = 0x011,
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};
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/*****************************************************************************/
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/* DDR SDRAM controller */
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#define SDRAM_DDR_BCR_MASK 0xFFDEE001
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static uint32_t sdram_ddr_bcr(hwaddr ram_base, hwaddr ram_size)
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{
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uint32_t bcr;
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switch (ram_size) {
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case 4 * MiB:
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bcr = 0;
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break;
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case 8 * MiB:
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bcr = 0x20000;
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break;
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case 16 * MiB:
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bcr = 0x40000;
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break;
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case 32 * MiB:
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bcr = 0x60000;
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break;
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case 64 * MiB:
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bcr = 0x80000;
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break;
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case 128 * MiB:
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bcr = 0xA0000;
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break;
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case 256 * MiB:
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bcr = 0xC0000;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: invalid RAM size 0x%" HWADDR_PRIx "\n", __func__,
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ram_size);
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return 0;
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}
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bcr |= ram_base & 0xFF800000;
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bcr |= 1;
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return bcr;
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}
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static inline hwaddr sdram_ddr_base(uint32_t bcr)
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{
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return bcr & 0xFF800000;
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}
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static hwaddr sdram_ddr_size(uint32_t bcr)
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{
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hwaddr size;
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int sh;
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sh = (bcr >> 17) & 0x7;
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if (sh == 7) {
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size = -1;
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} else {
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size = (4 * MiB) << sh;
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}
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return size;
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}
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static uint32_t sdram_ddr_dcr_read(void *opaque, int dcrn)
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{
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Ppc4xxSdramDdrState *s = opaque;
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uint32_t ret;
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switch (dcrn) {
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case SDRAM0_CFGADDR:
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ret = s->addr;
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break;
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case SDRAM0_CFGDATA:
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switch (s->addr) {
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case 0x00: /* SDRAM_BESR0 */
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ret = s->besr0;
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break;
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case 0x08: /* SDRAM_BESR1 */
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ret = s->besr1;
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break;
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case 0x10: /* SDRAM_BEAR */
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ret = s->bear;
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break;
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case 0x20: /* SDRAM_CFG */
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ret = s->cfg;
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break;
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case 0x24: /* SDRAM_STATUS */
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ret = s->status;
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break;
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case 0x30: /* SDRAM_RTR */
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ret = s->rtr;
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break;
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case 0x34: /* SDRAM_PMIT */
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ret = s->pmit;
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break;
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case 0x40: /* SDRAM_B0CR */
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ret = s->bank[0].bcr;
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break;
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case 0x44: /* SDRAM_B1CR */
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ret = s->bank[1].bcr;
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break;
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case 0x48: /* SDRAM_B2CR */
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ret = s->bank[2].bcr;
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break;
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case 0x4C: /* SDRAM_B3CR */
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ret = s->bank[3].bcr;
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break;
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case 0x80: /* SDRAM_TR */
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ret = -1; /* ? */
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break;
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case 0x94: /* SDRAM_ECCCFG */
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ret = s->ecccfg;
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break;
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case 0x98: /* SDRAM_ECCESR */
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ret = s->eccesr;
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break;
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default: /* Error */
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ret = -1;
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break;
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}
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break;
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default:
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/* Avoid gcc warning */
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ret = 0;
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break;
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}
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return ret;
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}
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static void sdram_ddr_dcr_write(void *opaque, int dcrn, uint32_t val)
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{
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Ppc4xxSdramDdrState *s = opaque;
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int i;
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switch (dcrn) {
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case SDRAM0_CFGADDR:
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s->addr = val;
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break;
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case SDRAM0_CFGDATA:
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switch (s->addr) {
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case 0x00: /* SDRAM_BESR0 */
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s->besr0 &= ~val;
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break;
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case 0x08: /* SDRAM_BESR1 */
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s->besr1 &= ~val;
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break;
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case 0x10: /* SDRAM_BEAR */
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s->bear = val;
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break;
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case 0x20: /* SDRAM_CFG */
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val &= 0xFFE00000;
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if (!(s->cfg & 0x80000000) && (val & 0x80000000)) {
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trace_ppc4xx_sdram_enable("enable");
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/* validate all RAM mappings */
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for (i = 0; i < s->nbanks; i++) {
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if (s->bank[i].size) {
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sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
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s->bank[i].base, s->bank[i].size,
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1);
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}
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}
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s->status &= ~0x80000000;
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} else if ((s->cfg & 0x80000000) && !(val & 0x80000000)) {
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trace_ppc4xx_sdram_enable("disable");
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/* invalidate all RAM mappings */
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for (i = 0; i < s->nbanks; i++) {
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if (s->bank[i].size) {
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sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
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s->bank[i].base, s->bank[i].size,
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0);
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}
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}
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s->status |= 0x80000000;
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}
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if (!(s->cfg & 0x40000000) && (val & 0x40000000)) {
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s->status |= 0x40000000;
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} else if ((s->cfg & 0x40000000) && !(val & 0x40000000)) {
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s->status &= ~0x40000000;
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}
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s->cfg = val;
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break;
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case 0x24: /* SDRAM_STATUS */
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/* Read-only register */
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break;
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case 0x30: /* SDRAM_RTR */
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s->rtr = val & 0x3FF80000;
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break;
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case 0x34: /* SDRAM_PMIT */
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s->pmit = (val & 0xF8000000) | 0x07C00000;
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break;
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case 0x40: /* SDRAM_B0CR */
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case 0x44: /* SDRAM_B1CR */
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case 0x48: /* SDRAM_B2CR */
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case 0x4C: /* SDRAM_B3CR */
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i = (s->addr - 0x40) / 4;
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val &= SDRAM_DDR_BCR_MASK;
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if (s->bank[i].size) {
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sdram_bank_set_bcr(&s->bank[i], val,
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sdram_ddr_base(val), sdram_ddr_size(val),
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s->cfg & 0x80000000);
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}
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break;
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case 0x80: /* SDRAM_TR */
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s->tr = val & 0x018FC01F;
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break;
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case 0x94: /* SDRAM_ECCCFG */
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s->ecccfg = val & 0x00F00000;
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break;
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case 0x98: /* SDRAM_ECCESR */
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val &= 0xFFF0F000;
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if (s->eccesr == 0 && val != 0) {
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qemu_irq_raise(s->irq);
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} else if (s->eccesr != 0 && val == 0) {
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qemu_irq_lower(s->irq);
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}
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s->eccesr = val;
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break;
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default: /* Error */
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break;
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}
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break;
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}
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}
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static void ppc4xx_sdram_ddr_reset(DeviceState *dev)
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{
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Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
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s->addr = 0;
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s->bear = 0;
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s->besr0 = 0; /* No error */
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s->besr1 = 0; /* No error */
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s->cfg = 0;
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s->ecccfg = 0; /* No ECC */
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s->eccesr = 0; /* No error */
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s->pmit = 0x07C00000;
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s->rtr = 0x05F00000;
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s->tr = 0x00854009;
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/* We pre-initialize RAM banks */
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s->status = 0;
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s->cfg = 0x00800000;
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}
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static void ppc4xx_sdram_ddr_realize(DeviceState *dev, Error **errp)
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{
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Ppc4xxSdramDdrState *s = PPC4xx_SDRAM_DDR(dev);
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Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
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const ram_addr_t valid_bank_sizes[] = {
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256 * MiB, 128 * MiB, 64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 4 * MiB, 0
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};
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int i;
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if (s->nbanks < 1 || s->nbanks > 4) {
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error_setg(errp, "Invalid number of RAM banks");
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return;
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}
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if (!s->dram_mr) {
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error_setg(errp, "Missing dram memory region");
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return;
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}
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if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
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valid_bank_sizes, errp)) {
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return;
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}
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for (i = 0; i < s->nbanks; i++) {
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if (s->bank[i].size) {
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s->bank[i].bcr = sdram_ddr_bcr(s->bank[i].base, s->bank[i].size);
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sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
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s->bank[i].base, s->bank[i].size, 0);
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} else {
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sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
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}
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trace_ppc4xx_sdram_init(sdram_ddr_base(s->bank[i].bcr),
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sdram_ddr_size(s->bank[i].bcr),
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s->bank[i].bcr);
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}
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sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq);
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ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
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s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
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ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
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s, &sdram_ddr_dcr_read, &sdram_ddr_dcr_write);
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}
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static Property ppc4xx_sdram_ddr_props[] = {
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DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION,
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MemoryRegion *),
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DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(oc);
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dc->realize = ppc4xx_sdram_ddr_realize;
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dc->reset = ppc4xx_sdram_ddr_reset;
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/* Reason: only works as function of a ppc4xx SoC */
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dc->user_creatable = false;
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device_class_set_props(dc, ppc4xx_sdram_ddr_props);
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}
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void ppc4xx_sdram_ddr_enable(Ppc4xxSdramDdrState *s)
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{
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sdram_ddr_dcr_write(s, SDRAM0_CFGADDR, 0x20);
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sdram_ddr_dcr_write(s, SDRAM0_CFGDATA, 0x80000000);
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}
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/*****************************************************************************/
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/* DDR2 SDRAM controller */
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#define SDRAM_DDR2_BCR_MASK 0xffe0ffc1
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enum {
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SDRAM_R0BAS = 0x40,
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SDRAM_R1BAS,
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SDRAM_R2BAS,
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SDRAM_R3BAS,
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SDRAM_CONF1HB = 0x45,
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SDRAM_PLBADDULL = 0x4a,
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SDRAM_CONF1LL = 0x4b,
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SDRAM_CONFPATHB = 0x4f,
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SDRAM_PLBADDUHB = 0x50,
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};
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static uint32_t sdram_ddr2_bcr(hwaddr ram_base, hwaddr ram_size)
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{
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uint32_t bcr;
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switch (ram_size) {
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case 8 * MiB:
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bcr = 0xffc0;
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break;
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case 16 * MiB:
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bcr = 0xff80;
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break;
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case 32 * MiB:
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bcr = 0xff00;
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break;
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case 64 * MiB:
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bcr = 0xfe00;
|
|
break;
|
|
case 128 * MiB:
|
|
bcr = 0xfc00;
|
|
break;
|
|
case 256 * MiB:
|
|
bcr = 0xf800;
|
|
break;
|
|
case 512 * MiB:
|
|
bcr = 0xf000;
|
|
break;
|
|
case 1 * GiB:
|
|
bcr = 0xe000;
|
|
break;
|
|
case 2 * GiB:
|
|
bcr = 0xc000;
|
|
break;
|
|
case 4 * GiB:
|
|
bcr = 0x8000;
|
|
break;
|
|
default:
|
|
error_report("invalid RAM size " TARGET_FMT_plx, ram_size);
|
|
return 0;
|
|
}
|
|
bcr |= ram_base >> 2 & 0xffe00000;
|
|
bcr |= 1;
|
|
|
|
return bcr;
|
|
}
|
|
|
|
static inline hwaddr sdram_ddr2_base(uint32_t bcr)
|
|
{
|
|
return (bcr & 0xffe00000) << 2;
|
|
}
|
|
|
|
static hwaddr sdram_ddr2_size(uint32_t bcr)
|
|
{
|
|
hwaddr size;
|
|
int sh;
|
|
|
|
sh = 1024 - ((bcr >> 6) & 0x3ff);
|
|
size = 8 * MiB * sh;
|
|
|
|
return size;
|
|
}
|
|
|
|
static uint32_t sdram_ddr2_dcr_read(void *opaque, int dcrn)
|
|
{
|
|
Ppc4xxSdramDdr2State *s = opaque;
|
|
uint32_t ret = 0;
|
|
|
|
switch (dcrn) {
|
|
case SDRAM_R0BAS:
|
|
case SDRAM_R1BAS:
|
|
case SDRAM_R2BAS:
|
|
case SDRAM_R3BAS:
|
|
if (s->bank[dcrn - SDRAM_R0BAS].size) {
|
|
ret = sdram_ddr2_bcr(s->bank[dcrn - SDRAM_R0BAS].base,
|
|
s->bank[dcrn - SDRAM_R0BAS].size);
|
|
}
|
|
break;
|
|
case SDRAM_CONF1HB:
|
|
case SDRAM_CONF1LL:
|
|
case SDRAM_CONFPATHB:
|
|
case SDRAM_PLBADDULL:
|
|
case SDRAM_PLBADDUHB:
|
|
break;
|
|
case SDRAM0_CFGADDR:
|
|
ret = s->addr;
|
|
break;
|
|
case SDRAM0_CFGDATA:
|
|
switch (s->addr) {
|
|
case 0x14: /* SDRAM_MCSTAT (405EX) */
|
|
case 0x1F:
|
|
ret = 0x80000000;
|
|
break;
|
|
case 0x21: /* SDRAM_MCOPT2 */
|
|
ret = s->mcopt2;
|
|
break;
|
|
case 0x40: /* SDRAM_MB0CF */
|
|
ret = 0x00008001;
|
|
break;
|
|
case 0x7A: /* SDRAM_DLCR */
|
|
ret = 0x02000000;
|
|
break;
|
|
case 0xE1: /* SDR0_DDR0 */
|
|
ret = SDR0_DDR0_DDRM_ENCODE(1) | SDR0_DDR0_DDRM_DDR1;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define SDRAM_DDR2_MCOPT2_DCEN BIT(27)
|
|
|
|
static void sdram_ddr2_dcr_write(void *opaque, int dcrn, uint32_t val)
|
|
{
|
|
Ppc4xxSdramDdr2State *s = opaque;
|
|
int i;
|
|
|
|
switch (dcrn) {
|
|
case SDRAM_R0BAS:
|
|
case SDRAM_R1BAS:
|
|
case SDRAM_R2BAS:
|
|
case SDRAM_R3BAS:
|
|
case SDRAM_CONF1HB:
|
|
case SDRAM_CONF1LL:
|
|
case SDRAM_CONFPATHB:
|
|
case SDRAM_PLBADDULL:
|
|
case SDRAM_PLBADDUHB:
|
|
break;
|
|
case SDRAM0_CFGADDR:
|
|
s->addr = val;
|
|
break;
|
|
case SDRAM0_CFGDATA:
|
|
switch (s->addr) {
|
|
case 0x00: /* B0CR */
|
|
break;
|
|
case 0x21: /* SDRAM_MCOPT2 */
|
|
if (!(s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
|
|
(val & SDRAM_DDR2_MCOPT2_DCEN)) {
|
|
trace_ppc4xx_sdram_enable("enable");
|
|
/* validate all RAM mappings */
|
|
for (i = 0; i < s->nbanks; i++) {
|
|
if (s->bank[i].size) {
|
|
sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
|
|
s->bank[i].base, s->bank[i].size,
|
|
1);
|
|
}
|
|
}
|
|
s->mcopt2 |= SDRAM_DDR2_MCOPT2_DCEN;
|
|
} else if ((s->mcopt2 & SDRAM_DDR2_MCOPT2_DCEN) &&
|
|
!(val & SDRAM_DDR2_MCOPT2_DCEN)) {
|
|
trace_ppc4xx_sdram_enable("disable");
|
|
/* invalidate all RAM mappings */
|
|
for (i = 0; i < s->nbanks; i++) {
|
|
if (s->bank[i].size) {
|
|
sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
|
|
s->bank[i].base, s->bank[i].size,
|
|
0);
|
|
}
|
|
}
|
|
s->mcopt2 &= ~SDRAM_DDR2_MCOPT2_DCEN;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
static void ppc4xx_sdram_ddr2_reset(DeviceState *dev)
|
|
{
|
|
Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
|
|
|
|
s->addr = 0;
|
|
s->mcopt2 = 0;
|
|
}
|
|
|
|
static void ppc4xx_sdram_ddr2_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Ppc4xxSdramDdr2State *s = PPC4xx_SDRAM_DDR2(dev);
|
|
Ppc4xxDcrDeviceState *dcr = PPC4xx_DCR_DEVICE(dev);
|
|
/*
|
|
* SoC also has 4 GiB but that causes problem with 32 bit
|
|
* builds (4*GiB overflows the 32 bit ram_addr_t).
|
|
*/
|
|
const ram_addr_t valid_bank_sizes[] = {
|
|
2 * GiB, 1 * GiB, 512 * MiB, 256 * MiB, 128 * MiB,
|
|
64 * MiB, 32 * MiB, 16 * MiB, 8 * MiB, 0
|
|
};
|
|
int i;
|
|
|
|
if (s->nbanks < 1 || s->nbanks > 4) {
|
|
error_setg(errp, "Invalid number of RAM banks");
|
|
return;
|
|
}
|
|
if (!s->dram_mr) {
|
|
error_setg(errp, "Missing dram memory region");
|
|
return;
|
|
}
|
|
if (!ppc4xx_sdram_banks(s->dram_mr, s->nbanks, s->bank,
|
|
valid_bank_sizes, errp)) {
|
|
return;
|
|
}
|
|
for (i = 0; i < s->nbanks; i++) {
|
|
if (s->bank[i].size) {
|
|
s->bank[i].bcr = sdram_ddr2_bcr(s->bank[i].base, s->bank[i].size);
|
|
s->bank[i].bcr &= SDRAM_DDR2_BCR_MASK;
|
|
sdram_bank_set_bcr(&s->bank[i], s->bank[i].bcr,
|
|
s->bank[i].base, s->bank[i].size, 0);
|
|
} else {
|
|
sdram_bank_set_bcr(&s->bank[i], 0, 0, 0, 0);
|
|
}
|
|
trace_ppc4xx_sdram_init(sdram_ddr2_base(s->bank[i].bcr),
|
|
sdram_ddr2_size(s->bank[i].bcr),
|
|
s->bank[i].bcr);
|
|
}
|
|
|
|
ppc4xx_dcr_register(dcr, SDRAM0_CFGADDR,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM0_CFGDATA,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
|
|
ppc4xx_dcr_register(dcr, SDRAM_R0BAS,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_R1BAS,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_R2BAS,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_R3BAS,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_CONF1HB,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_PLBADDULL,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_CONF1LL,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_CONFPATHB,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
ppc4xx_dcr_register(dcr, SDRAM_PLBADDUHB,
|
|
s, &sdram_ddr2_dcr_read, &sdram_ddr2_dcr_write);
|
|
}
|
|
|
|
static Property ppc4xx_sdram_ddr2_props[] = {
|
|
DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = ppc4xx_sdram_ddr2_realize;
|
|
dc->reset = ppc4xx_sdram_ddr2_reset;
|
|
/* Reason: only works as function of a ppc4xx SoC */
|
|
dc->user_creatable = false;
|
|
device_class_set_props(dc, ppc4xx_sdram_ddr2_props);
|
|
}
|
|
|
|
void ppc4xx_sdram_ddr2_enable(Ppc4xxSdramDdr2State *s)
|
|
{
|
|
sdram_ddr2_dcr_write(s, SDRAM0_CFGADDR, 0x21);
|
|
sdram_ddr2_dcr_write(s, SDRAM0_CFGDATA, 0x08000000);
|
|
}
|
|
|
|
static const TypeInfo ppc4xx_sdram_types[] = {
|
|
{
|
|
.name = TYPE_PPC4xx_SDRAM_DDR,
|
|
.parent = TYPE_PPC4xx_DCR_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxSdramDdrState),
|
|
.class_init = ppc4xx_sdram_ddr_class_init,
|
|
}, {
|
|
.name = TYPE_PPC4xx_SDRAM_DDR2,
|
|
.parent = TYPE_PPC4xx_DCR_DEVICE,
|
|
.instance_size = sizeof(Ppc4xxSdramDdr2State),
|
|
.class_init = ppc4xx_sdram_ddr2_class_init,
|
|
}
|
|
};
|
|
|
|
DEFINE_TYPES(ppc4xx_sdram_types)
|