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760 lines
24 KiB
C
760 lines
24 KiB
C
/*
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* QEMU Motorla 680x0 Macintosh hardware System Emulator
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qemu/datadir.h"
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#include "qemu/guest-random.h"
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#include "sysemu/sysemu.h"
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#include "cpu.h"
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#include "hw/boards.h"
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#include "hw/or-irq.h"
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#include "hw/nmi.h"
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#include "elf.h"
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#include "hw/loader.h"
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#include "ui/console.h"
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#include "hw/char/escc.h"
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#include "hw/sysbus.h"
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#include "hw/scsi/esp.h"
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#include "standard-headers/asm-m68k/bootinfo.h"
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#include "standard-headers/asm-m68k/bootinfo-mac.h"
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#include "bootinfo.h"
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#include "hw/misc/mac_via.h"
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#include "hw/input/adb.h"
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#include "hw/nubus/mac-nubus-bridge.h"
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#include "hw/display/macfb.h"
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#include "hw/block/swim.h"
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#include "net/net.h"
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#include "qapi/error.h"
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#include "sysemu/qtest.h"
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#include "sysemu/runstate.h"
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#include "sysemu/reset.h"
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#include "migration/vmstate.h"
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#define MACROM_ADDR 0x40800000
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#define MACROM_SIZE 0x00100000
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#define MACROM_FILENAME "MacROM.bin"
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#define IO_BASE 0x50000000
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#define IO_SLICE 0x00040000
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#define IO_SIZE 0x04000000
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#define VIA_BASE (IO_BASE + 0x00000)
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#define SONIC_PROM_BASE (IO_BASE + 0x08000)
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#define SONIC_BASE (IO_BASE + 0x0a000)
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#define SCC_BASE (IO_BASE + 0x0c020)
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#define ESP_BASE (IO_BASE + 0x10000)
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#define ESP_PDMA (IO_BASE + 0x10100)
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#define ASC_BASE (IO_BASE + 0x14000)
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#define SWIM_BASE (IO_BASE + 0x1E000)
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#define SONIC_PROM_SIZE 0x1000
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/*
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* the video base, whereas it a Nubus address,
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* is needed by the kernel to have early display and
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* thus provided by the bootloader
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*/
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#define VIDEO_BASE 0xf9000000
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#define MAC_CLOCK 3686418
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/*
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* Slot 0x9 is reserved for use by the in-built framebuffer whilst only
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* slots 0xc, 0xd and 0xe physically exist on the Quadra 800
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*/
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#define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \
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BIT(0xe))
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/*
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* The GLUE (General Logic Unit) is an Apple custom integrated circuit chip
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* that performs a variety of functions (RAM management, clock generation, ...).
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* The GLUE chip receives interrupt requests from various devices,
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* assign priority to each, and asserts one or more interrupt line to the
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* CPU.
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*/
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#define TYPE_GLUE "q800-glue"
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OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE)
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struct GLUEState {
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SysBusDevice parent_obj;
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M68kCPU *cpu;
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uint8_t ipr;
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uint8_t auxmode;
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qemu_irq irqs[1];
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QEMUTimer *nmi_release;
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};
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#define GLUE_IRQ_IN_VIA1 0
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#define GLUE_IRQ_IN_VIA2 1
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#define GLUE_IRQ_IN_SONIC 2
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#define GLUE_IRQ_IN_ESCC 3
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#define GLUE_IRQ_IN_NMI 4
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#define GLUE_IRQ_NUBUS_9 0
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/*
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* The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes
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* controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented
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* in NetBSD as follows:
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*
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* A/UX mode (Linux, NetBSD, auxmode GPIO low)
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*
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* Level 0: Spurious: ignored
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* Level 1: Software
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* Level 2: VIA2 (except ethernet, sound)
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* Level 3: Ethernet
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* Level 4: Serial (SCC)
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* Level 5: Sound
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* Level 6: VIA1
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* Level 7: NMIs: parity errors, RESET button, YANCC error
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*
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* Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high)
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*
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* Level 0: Spurious: ignored
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* Level 1: VIA1 (clock, ADB)
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* Level 2: VIA2 (NuBus, SCSI)
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* Level 3:
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* Level 4: Serial (SCC)
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* Level 5:
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* Level 6:
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* Level 7: Non-maskable: parity errors, RESET button
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*
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* Note that despite references to A/UX mode in Linux and NetBSD, at least
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* A/UX 3.0.1 still uses Classic mode.
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*/
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static void GLUE_set_irq(void *opaque, int irq, int level)
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{
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GLUEState *s = opaque;
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int i;
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if (s->auxmode) {
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/* Classic mode */
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switch (irq) {
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case GLUE_IRQ_IN_VIA1:
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irq = 0;
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break;
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case GLUE_IRQ_IN_VIA2:
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irq = 1;
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break;
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case GLUE_IRQ_IN_SONIC:
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/* Route to VIA2 instead */
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qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level);
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return;
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case GLUE_IRQ_IN_ESCC:
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irq = 3;
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break;
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case GLUE_IRQ_IN_NMI:
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irq = 6;
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break;
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default:
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g_assert_not_reached();
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}
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} else {
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/* A/UX mode */
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switch (irq) {
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case GLUE_IRQ_IN_VIA1:
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irq = 5;
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break;
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case GLUE_IRQ_IN_VIA2:
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irq = 1;
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break;
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case GLUE_IRQ_IN_SONIC:
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irq = 2;
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break;
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case GLUE_IRQ_IN_ESCC:
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irq = 3;
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break;
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case GLUE_IRQ_IN_NMI:
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irq = 6;
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break;
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default:
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g_assert_not_reached();
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}
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}
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if (level) {
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s->ipr |= 1 << irq;
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} else {
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s->ipr &= ~(1 << irq);
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}
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for (i = 7; i >= 0; i--) {
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if ((s->ipr >> i) & 1) {
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m68k_set_irq_level(s->cpu, i + 1, i + 25);
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return;
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}
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}
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m68k_set_irq_level(s->cpu, 0, 0);
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}
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static void glue_auxmode_set_irq(void *opaque, int irq, int level)
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{
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GLUEState *s = GLUE(opaque);
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s->auxmode = level;
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}
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static void glue_nmi(NMIState *n, int cpu_index, Error **errp)
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{
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GLUEState *s = GLUE(n);
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/* Hold NMI active for 100ms */
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GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1);
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timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100);
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}
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static void glue_nmi_release(void *opaque)
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{
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GLUEState *s = GLUE(opaque);
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GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0);
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}
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static void glue_reset(DeviceState *dev)
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{
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GLUEState *s = GLUE(dev);
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s->ipr = 0;
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s->auxmode = 0;
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timer_del(s->nmi_release);
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}
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static const VMStateDescription vmstate_glue = {
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.name = "q800-glue",
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.version_id = 0,
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.minimum_version_id = 0,
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.fields = (VMStateField[]) {
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VMSTATE_UINT8(ipr, GLUEState),
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VMSTATE_UINT8(auxmode, GLUEState),
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VMSTATE_TIMER_PTR(nmi_release, GLUEState),
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VMSTATE_END_OF_LIST(),
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},
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};
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/*
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* If the m68k CPU implemented its inbound irq lines as GPIO lines
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* rather than via the m68k_set_irq_level() function we would not need
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* this cpu link property and could instead provide outbound IRQ lines
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* that the board could wire up to the CPU.
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*/
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static Property glue_properties[] = {
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DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void glue_finalize(Object *obj)
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{
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GLUEState *s = GLUE(obj);
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timer_free(s->nmi_release);
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}
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static void glue_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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GLUEState *s = GLUE(dev);
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qdev_init_gpio_in(dev, GLUE_set_irq, 8);
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qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1);
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qdev_init_gpio_out(dev, s->irqs, 1);
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/* NMI release timer */
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s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s);
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}
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static void glue_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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NMIClass *nc = NMI_CLASS(klass);
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dc->vmsd = &vmstate_glue;
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dc->reset = glue_reset;
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device_class_set_props(dc, glue_properties);
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nc->nmi_monitor_handler = glue_nmi;
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}
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static const TypeInfo glue_info = {
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.name = TYPE_GLUE,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(GLUEState),
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.instance_init = glue_init,
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.instance_finalize = glue_finalize,
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.class_init = glue_class_init,
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.interfaces = (InterfaceInfo[]) {
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{ TYPE_NMI },
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{ }
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},
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};
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static void main_cpu_reset(void *opaque)
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{
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M68kCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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cpu->env.aregs[7] = ldl_phys(cs->as, 0);
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cpu->env.pc = ldl_phys(cs->as, 4);
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}
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static void rerandomize_rng_seed(void *opaque)
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{
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struct bi_record *rng_seed = opaque;
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qemu_guest_getrandom_nofail((void *)rng_seed->data + 2,
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be16_to_cpu(*(uint16_t *)rng_seed->data));
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}
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static uint8_t fake_mac_rom[] = {
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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/* offset: 0xa - mac_reset */
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/* via2[vDirB] |= VIA2B_vPower */
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0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */
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0x10, 0x10, /* moveb %a0@,%d0 */
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0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */
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0x10, 0x80, /* moveb %d0,%a0@ */
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/* via2[vBufB] &= ~VIA2B_vPower */
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0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */
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0x10, 0x10, /* moveb %a0@,%d0 */
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0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */
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0x10, 0x80, /* moveb %d0,%a0@ */
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/* while (true) ; */
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0x60, 0xFE /* bras [self] */
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};
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static void q800_init(MachineState *machine)
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{
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M68kCPU *cpu = NULL;
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int linux_boot;
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int32_t kernel_size;
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uint64_t elf_entry;
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char *filename;
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int bios_size;
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ram_addr_t initrd_base;
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int32_t initrd_size;
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MemoryRegion *rom;
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MemoryRegion *io;
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MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1);
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uint8_t *prom;
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const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1;
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int i, checksum;
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MacFbMode *macfb_mode;
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ram_addr_t ram_size = machine->ram_size;
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const char *kernel_filename = machine->kernel_filename;
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const char *initrd_filename = machine->initrd_filename;
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const char *kernel_cmdline = machine->kernel_cmdline;
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const char *bios_name = machine->firmware ?: MACROM_FILENAME;
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hwaddr parameters_base;
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CPUState *cs;
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DeviceState *dev;
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DeviceState *via1_dev, *via2_dev;
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DeviceState *escc_orgate;
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SysBusESPState *sysbus_esp;
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ESPState *esp;
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SysBusDevice *sysbus;
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BusState *adb_bus;
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NubusBus *nubus;
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DeviceState *glue;
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DriveInfo *dinfo;
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uint8_t rng_seed[32];
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linux_boot = (kernel_filename != NULL);
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if (ram_size > 1 * GiB) {
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error_report("Too much memory for this machine: %" PRId64 " MiB, "
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"maximum 1024 MiB", ram_size / MiB);
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exit(1);
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}
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/* init CPUs */
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cpu = M68K_CPU(cpu_create(machine->cpu_type));
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qemu_register_reset(main_cpu_reset, cpu);
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/* RAM */
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memory_region_add_subregion(get_system_memory(), 0, machine->ram);
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/*
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* Memory from IO_BASE to IO_BASE + IO_SLICE is repeated
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* from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE
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*/
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io = g_new(MemoryRegion, io_slice_nb);
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for (i = 0; i < io_slice_nb; i++) {
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char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1);
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memory_region_init_alias(&io[i], NULL, name, get_system_memory(),
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IO_BASE, IO_SLICE);
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memory_region_add_subregion(get_system_memory(),
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IO_BASE + (i + 1) * IO_SLICE, &io[i]);
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g_free(name);
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}
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/* IRQ Glue */
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glue = qdev_new(TYPE_GLUE);
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object_property_set_link(OBJECT(glue), "cpu", OBJECT(cpu), &error_abort);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal);
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/* VIA 1 */
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via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1);
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dinfo = drive_get(IF_MTD, 0, 0);
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if (dinfo) {
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qdev_prop_set_drive(via1_dev, "drive", blk_by_legacy_dinfo(dinfo));
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}
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sysbus = SYS_BUS_DEVICE(via1_dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 1, VIA_BASE);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1));
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/* A/UX mode */
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qdev_connect_gpio_out(via1_dev, 0,
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qdev_get_gpio_in_named(glue, "auxmode", 0));
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adb_bus = qdev_get_child_bus(via1_dev, "adb.0");
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dev = qdev_new(TYPE_ADB_KEYBOARD);
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qdev_realize_and_unref(dev, adb_bus, &error_fatal);
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dev = qdev_new(TYPE_ADB_MOUSE);
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qdev_realize_and_unref(dev, adb_bus, &error_fatal);
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/* VIA 2 */
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via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2);
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sysbus = SYS_BUS_DEVICE(via2_dev);
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sysbus_realize_and_unref(sysbus, &error_fatal);
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sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE);
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sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2));
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/* MACSONIC */
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if (nb_nics > 1) {
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error_report("q800 can only have one ethernet interface");
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exit(1);
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}
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qemu_check_nic_model(&nd_table[0], "dp83932");
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/*
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* MacSonic driver needs an Apple MAC address
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* Valid prefix are:
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* 00:05:02 Apple
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* 00:80:19 Dayna Communications, Inc.
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* 00:A0:40 Apple
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* 08:00:07 Apple
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* (Q800 use the last one)
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*/
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nd_table[0].macaddr.a[0] = 0x08;
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nd_table[0].macaddr.a[1] = 0x00;
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nd_table[0].macaddr.a[2] = 0x07;
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dev = qdev_new("dp8393x");
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qdev_set_nic_properties(dev, &nd_table[0]);
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qdev_prop_set_uint8(dev, "it_shift", 2);
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|
qdev_prop_set_bit(dev, "big_endian", true);
|
|
object_property_set_link(OBJECT(dev), "dma_mr",
|
|
OBJECT(get_system_memory()), &error_abort);
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
|
sysbus_realize_and_unref(sysbus, &error_fatal);
|
|
sysbus_mmio_map(sysbus, 0, SONIC_BASE);
|
|
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC));
|
|
|
|
memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom",
|
|
SONIC_PROM_SIZE, &error_fatal);
|
|
memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE,
|
|
dp8393x_prom);
|
|
|
|
/* Add MAC address with valid checksum to PROM */
|
|
prom = memory_region_get_ram_ptr(dp8393x_prom);
|
|
checksum = 0;
|
|
for (i = 0; i < 6; i++) {
|
|
prom[i] = revbit8(nd_table[0].macaddr.a[i]);
|
|
checksum ^= prom[i];
|
|
}
|
|
prom[7] = 0xff - checksum;
|
|
|
|
/* SCC */
|
|
|
|
dev = qdev_new(TYPE_ESCC);
|
|
qdev_prop_set_uint32(dev, "disabled", 0);
|
|
qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK);
|
|
qdev_prop_set_uint32(dev, "it_shift", 1);
|
|
qdev_prop_set_bit(dev, "bit_swap", true);
|
|
qdev_prop_set_chr(dev, "chrA", serial_hd(0));
|
|
qdev_prop_set_chr(dev, "chrB", serial_hd(1));
|
|
qdev_prop_set_uint32(dev, "chnBtype", 0);
|
|
qdev_prop_set_uint32(dev, "chnAtype", 0);
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
|
sysbus_realize_and_unref(sysbus, &error_fatal);
|
|
|
|
/* Logically OR both its IRQs together */
|
|
escc_orgate = DEVICE(object_new(TYPE_OR_IRQ));
|
|
object_property_set_int(OBJECT(escc_orgate), "num-lines", 2, &error_fatal);
|
|
qdev_realize_and_unref(escc_orgate, NULL, &error_fatal);
|
|
sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0));
|
|
sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1));
|
|
qdev_connect_gpio_out(DEVICE(escc_orgate), 0,
|
|
qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC));
|
|
sysbus_mmio_map(sysbus, 0, SCC_BASE);
|
|
|
|
/* SCSI */
|
|
|
|
dev = qdev_new(TYPE_SYSBUS_ESP);
|
|
sysbus_esp = SYSBUS_ESP(dev);
|
|
esp = &sysbus_esp->esp;
|
|
esp->dma_memory_read = NULL;
|
|
esp->dma_memory_write = NULL;
|
|
esp->dma_opaque = NULL;
|
|
sysbus_esp->it_shift = 4;
|
|
esp->dma_enabled = 1;
|
|
|
|
sysbus = SYS_BUS_DEVICE(dev);
|
|
sysbus_realize_and_unref(sysbus, &error_fatal);
|
|
/* SCSI and SCSI data IRQs are negative edge triggered */
|
|
sysbus_connect_irq(sysbus, 0, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
|
|
VIA2_IRQ_SCSI_BIT)));
|
|
sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev,
|
|
VIA2_IRQ_SCSI_DATA_BIT)));
|
|
sysbus_mmio_map(sysbus, 0, ESP_BASE);
|
|
sysbus_mmio_map(sysbus, 1, ESP_PDMA);
|
|
|
|
scsi_bus_legacy_handle_cmdline(&esp->bus);
|
|
|
|
/* SWIM floppy controller */
|
|
|
|
dev = qdev_new(TYPE_SWIM);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE);
|
|
|
|
/* NuBus */
|
|
|
|
dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE);
|
|
qdev_prop_set_uint32(dev, "slot-available-mask",
|
|
Q800_NUBUS_SLOTS_AVAILABLE);
|
|
sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0,
|
|
MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE);
|
|
sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE +
|
|
MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE);
|
|
qdev_connect_gpio_out(dev, 9,
|
|
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
|
|
VIA2_NUBUS_IRQ_INTVIDEO));
|
|
for (i = 1; i < VIA2_NUBUS_IRQ_NB; i++) {
|
|
qdev_connect_gpio_out(dev, 9 + i,
|
|
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
|
|
VIA2_NUBUS_IRQ_9 + i));
|
|
}
|
|
|
|
/*
|
|
* Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused
|
|
* IRQ via GLUE for use by SONIC Ethernet in classic mode
|
|
*/
|
|
qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9,
|
|
qdev_get_gpio_in_named(via2_dev, "nubus-irq",
|
|
VIA2_NUBUS_IRQ_9));
|
|
|
|
nubus = &NUBUS_BRIDGE(dev)->bus;
|
|
|
|
/* framebuffer in nubus slot #9 */
|
|
|
|
dev = qdev_new(TYPE_NUBUS_MACFB);
|
|
qdev_prop_set_uint32(dev, "slot", 9);
|
|
qdev_prop_set_uint32(dev, "width", graphic_width);
|
|
qdev_prop_set_uint32(dev, "height", graphic_height);
|
|
qdev_prop_set_uint8(dev, "depth", graphic_depth);
|
|
if (graphic_width == 1152 && graphic_height == 870) {
|
|
qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_APPLE_21_COLOR);
|
|
} else {
|
|
qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_VGA);
|
|
}
|
|
qdev_realize_and_unref(dev, BUS(nubus), &error_fatal);
|
|
|
|
macfb_mode = (NUBUS_MACFB(dev)->macfb).mode;
|
|
|
|
cs = CPU(cpu);
|
|
if (linux_boot) {
|
|
uint64_t high;
|
|
void *param_blob, *param_ptr, *param_rng_seed;
|
|
|
|
if (kernel_cmdline) {
|
|
param_blob = g_malloc(strlen(kernel_cmdline) + 1024);
|
|
} else {
|
|
param_blob = g_malloc(1024);
|
|
}
|
|
|
|
kernel_size = load_elf(kernel_filename, NULL, NULL, NULL,
|
|
&elf_entry, NULL, &high, NULL, 1,
|
|
EM_68K, 0, 0);
|
|
if (kernel_size < 0) {
|
|
error_report("could not load kernel '%s'", kernel_filename);
|
|
exit(1);
|
|
}
|
|
stl_phys(cs->as, 4, elf_entry); /* reset initial PC */
|
|
parameters_base = (high + 1) & ~1;
|
|
param_ptr = param_blob;
|
|
|
|
BOOTINFO1(param_ptr, BI_MACHTYPE, MACH_MAC);
|
|
BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040);
|
|
BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040);
|
|
BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040);
|
|
BOOTINFO1(param_ptr, BI_MAC_CPUID, CPUB_68040);
|
|
BOOTINFO1(param_ptr, BI_MAC_MODEL, MAC_MODEL_Q800);
|
|
BOOTINFO1(param_ptr,
|
|
BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */
|
|
BOOTINFO2(param_ptr, BI_MEMCHUNK, 0, ram_size);
|
|
BOOTINFO1(param_ptr, BI_MAC_VADDR,
|
|
VIDEO_BASE + macfb_mode->offset);
|
|
BOOTINFO1(param_ptr, BI_MAC_VDEPTH, graphic_depth);
|
|
BOOTINFO1(param_ptr, BI_MAC_VDIM,
|
|
(graphic_height << 16) | graphic_width);
|
|
BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride);
|
|
BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE);
|
|
|
|
rom = g_malloc(sizeof(*rom));
|
|
memory_region_init_ram_ptr(rom, NULL, "m68k_fake_mac.rom",
|
|
sizeof(fake_mac_rom), fake_mac_rom);
|
|
memory_region_set_readonly(rom, true);
|
|
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
|
|
|
|
if (kernel_cmdline) {
|
|
BOOTINFOSTR(param_ptr, BI_COMMAND_LINE,
|
|
kernel_cmdline);
|
|
}
|
|
|
|
/* Pass seed to RNG. */
|
|
param_rng_seed = param_ptr;
|
|
qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
|
|
BOOTINFODATA(param_ptr, BI_RNG_SEED,
|
|
rng_seed, sizeof(rng_seed));
|
|
|
|
/* load initrd */
|
|
if (initrd_filename) {
|
|
initrd_size = get_image_size(initrd_filename);
|
|
if (initrd_size < 0) {
|
|
error_report("could not load initial ram disk '%s'",
|
|
initrd_filename);
|
|
exit(1);
|
|
}
|
|
|
|
initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK;
|
|
load_image_targphys(initrd_filename, initrd_base,
|
|
ram_size - initrd_base);
|
|
BOOTINFO2(param_ptr, BI_RAMDISK, initrd_base,
|
|
initrd_size);
|
|
} else {
|
|
initrd_base = 0;
|
|
initrd_size = 0;
|
|
}
|
|
BOOTINFO0(param_ptr, BI_LAST);
|
|
rom_add_blob_fixed_as("bootinfo", param_blob, param_ptr - param_blob,
|
|
parameters_base, cs->as);
|
|
qemu_register_reset_nosnapshotload(rerandomize_rng_seed,
|
|
rom_ptr_for_as(cs->as, parameters_base,
|
|
param_ptr - param_blob) +
|
|
(param_rng_seed - param_blob));
|
|
g_free(param_blob);
|
|
} else {
|
|
uint8_t *ptr;
|
|
/* allocate and load BIOS */
|
|
rom = g_malloc(sizeof(*rom));
|
|
memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE,
|
|
&error_abort);
|
|
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
|
|
memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom);
|
|
|
|
/* Load MacROM binary */
|
|
if (filename) {
|
|
bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE);
|
|
g_free(filename);
|
|
} else {
|
|
bios_size = -1;
|
|
}
|
|
|
|
/* Remove qtest_enabled() check once firmware files are in the tree */
|
|
if (!qtest_enabled()) {
|
|
if (bios_size <= 0 || bios_size > MACROM_SIZE) {
|
|
error_report("could not load MacROM '%s'", bios_name);
|
|
exit(1);
|
|
}
|
|
|
|
ptr = rom_ptr(MACROM_ADDR, bios_size);
|
|
assert(ptr != NULL);
|
|
stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */
|
|
stl_phys(cs->as, 4,
|
|
MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */
|
|
}
|
|
}
|
|
}
|
|
|
|
static GlobalProperty hw_compat_q800[] = {
|
|
{ "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on"},
|
|
{ "scsi-hd", "vendor", " SEAGATE" },
|
|
{ "scsi-hd", "product", " ST225N" },
|
|
{ "scsi-hd", "ver", "1.0 " },
|
|
{ "scsi-cd", "quirk_mode_page_apple_vendor", "on"},
|
|
{ "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on"},
|
|
{ "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on"},
|
|
{ "scsi-cd", "quirk_mode_page_truncated", "on"},
|
|
{ "scsi-cd", "vendor", "MATSHITA" },
|
|
{ "scsi-cd", "product", "CD-ROM CR-8005" },
|
|
{ "scsi-cd", "ver", "1.0k" },
|
|
};
|
|
static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800);
|
|
|
|
static void q800_machine_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
MachineClass *mc = MACHINE_CLASS(oc);
|
|
mc->desc = "Macintosh Quadra 800";
|
|
mc->init = q800_init;
|
|
mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040");
|
|
mc->max_cpus = 1;
|
|
mc->block_default_type = IF_SCSI;
|
|
mc->default_ram_id = "m68k_mac.ram";
|
|
compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len);
|
|
}
|
|
|
|
static const TypeInfo q800_machine_typeinfo = {
|
|
.name = MACHINE_TYPE_NAME("q800"),
|
|
.parent = TYPE_MACHINE,
|
|
.class_init = q800_machine_class_init,
|
|
};
|
|
|
|
static void q800_machine_register_types(void)
|
|
{
|
|
type_register_static(&q800_machine_typeinfo);
|
|
type_register_static(&glue_info);
|
|
}
|
|
|
|
type_init(q800_machine_register_types)
|