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916 lines
30 KiB
C
916 lines
30 KiB
C
/*
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* ARM GICv3 emulation: Distributor
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*
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2016 Linaro Limited.
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* Written by Shlomo Pongratz, Peter Maydell
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*
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* This code is licensed under the GPL, version 2 or (at your option)
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* any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "trace.h"
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#include "gicv3_internal.h"
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/* The GICD_NSACR registers contain a two bit field for each interrupt which
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* allows the guest to give NonSecure code access to registers controlling
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* Secure interrupts:
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* 0b00: no access (NS accesses to bits for Secure interrupts will RAZ/WI)
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* 0b01: NS r/w accesses permitted to ISPENDR, SETSPI_NSR, SGIR
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* 0b10: as 0b01, and also r/w to ICPENDR, r/o to ISACTIVER/ICACTIVER,
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* and w/o to CLRSPI_NSR
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* 0b11: as 0b10, and also r/w to IROUTER and ITARGETSR
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*
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* Given a (multiple-of-32) interrupt number, these mask functions return
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* a mask word where each bit is 1 if the NSACR settings permit access
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* to the interrupt. The mask returned can then be ORed with the GICD_GROUP
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* word for this set of interrupts to give an overall mask.
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*/
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typedef uint32_t maskfn(GICv3State *s, int irq);
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static uint32_t mask_nsacr_ge1(GICv3State *s, int irq)
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{
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/* Return a mask where each bit is set if the NSACR field is >= 1 */
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uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
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raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
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raw_nsacr = (raw_nsacr >> 1) | raw_nsacr;
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return half_unshuffle64(raw_nsacr);
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}
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static uint32_t mask_nsacr_ge2(GICv3State *s, int irq)
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{
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/* Return a mask where each bit is set if the NSACR field is >= 2 */
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uint64_t raw_nsacr = s->gicd_nsacr[irq / 16 + 1];
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raw_nsacr = raw_nsacr << 32 | s->gicd_nsacr[irq / 16];
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raw_nsacr = raw_nsacr >> 1;
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return half_unshuffle64(raw_nsacr);
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}
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/* We don't need a mask_nsacr_ge3() because IROUTER<n> isn't a bitmap register,
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* but it would be implemented using:
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* raw_nsacr = (raw_nsacr >> 1) & raw_nsacr;
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*/
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static uint32_t mask_group_and_nsacr(GICv3State *s, MemTxAttrs attrs,
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maskfn *maskfn, int irq)
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{
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/* Return a 32-bit mask which should be applied for this set of 32
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* interrupts; each bit is 1 if access is permitted by the
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* combination of attrs.secure, GICD_GROUPR and GICD_NSACR.
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*/
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uint32_t mask;
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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/* bits for Group 0 or Secure Group 1 interrupts are RAZ/WI
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* unless the NSACR bits permit access.
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*/
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mask = *gic_bmp_ptr32(s->group, irq);
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if (maskfn) {
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mask |= maskfn(s, irq);
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}
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return mask;
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}
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return 0xFFFFFFFFU;
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}
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static int gicd_ns_access(GICv3State *s, int irq)
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{
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/* Return the 2 bit NS_access<x> field from GICD_NSACR<n> for the
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* specified interrupt.
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*/
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return 0;
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}
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return extract32(s->gicd_nsacr[irq / 16], (irq % 16) * 2, 2);
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}
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static void gicd_write_set_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
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uint32_t *bmp,
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maskfn *maskfn,
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int offset, uint32_t val)
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{
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/* Helper routine to implement writing to a "set-bitmap" register
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* (GICD_ISENABLER, GICD_ISPENDR, etc).
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* Semantics implemented here:
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* RAZ/WI for SGIs, PPIs, unimplemented IRQs
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* Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
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* Writing 1 means "set bit in bitmap"; writing 0 is ignored.
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* offset should be the offset in bytes of the register from the start
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* of its group.
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*/
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int irq = offset * 8;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return;
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}
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val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
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*gic_bmp_ptr32(bmp, irq) |= val;
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gicv3_update(s, irq, 32);
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}
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static void gicd_write_clear_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
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uint32_t *bmp,
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maskfn *maskfn,
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int offset, uint32_t val)
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{
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/* Helper routine to implement writing to a "clear-bitmap" register
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* (GICD_ICENABLER, GICD_ICPENDR, etc).
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* Semantics implemented here:
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* RAZ/WI for SGIs, PPIs, unimplemented IRQs
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* Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
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* Writing 1 means "clear bit in bitmap"; writing 0 is ignored.
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* offset should be the offset in bytes of the register from the start
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* of its group.
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*/
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int irq = offset * 8;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return;
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}
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val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
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*gic_bmp_ptr32(bmp, irq) &= ~val;
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gicv3_update(s, irq, 32);
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}
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static uint32_t gicd_read_bitmap_reg(GICv3State *s, MemTxAttrs attrs,
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uint32_t *bmp,
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maskfn *maskfn,
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int offset)
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{
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/* Helper routine to implement reading a "set/clear-bitmap" register
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* (GICD_ICENABLER, GICD_ISENABLER, GICD_ICPENDR, etc).
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* Semantics implemented here:
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* RAZ/WI for SGIs, PPIs, unimplemented IRQs
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* Bits corresponding to Group 0 or Secure Group 1 interrupts RAZ/WI.
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* offset should be the offset in bytes of the register from the start
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* of its group.
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*/
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int irq = offset * 8;
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uint32_t val;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return 0;
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}
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val = *gic_bmp_ptr32(bmp, irq);
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if (bmp == s->pending) {
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/* The PENDING register is a special case -- for level triggered
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* interrupts, the PENDING state is the logical OR of the state of
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* the PENDING latch with the input line level.
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*/
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uint32_t edge = *gic_bmp_ptr32(s->edge_trigger, irq);
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uint32_t level = *gic_bmp_ptr32(s->level, irq);
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val |= (~edge & level);
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}
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val &= mask_group_and_nsacr(s, attrs, maskfn, irq);
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return val;
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}
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static uint8_t gicd_read_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq)
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{
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/* Read the value of GICD_IPRIORITYR<n> for the specified interrupt,
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* honouring security state (these are RAZ/WI for Group 0 or Secure
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* Group 1 interrupts).
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*/
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uint32_t prio;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return 0;
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}
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prio = s->gicd_ipriority[irq];
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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if (!gicv3_gicd_group_test(s, irq)) {
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/* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
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return 0;
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}
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/* NS view of the interrupt priority */
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prio = (prio << 1) & 0xff;
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}
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return prio;
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}
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static void gicd_write_ipriorityr(GICv3State *s, MemTxAttrs attrs, int irq,
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uint8_t value)
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{
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/* Write the value of GICD_IPRIORITYR<n> for the specified interrupt,
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* honouring security state (these are RAZ/WI for Group 0 or Secure
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* Group 1 interrupts).
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*/
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return;
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}
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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if (!gicv3_gicd_group_test(s, irq)) {
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/* Fields for Group 0 or Secure Group 1 interrupts are RAZ/WI */
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return;
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}
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/* NS view of the interrupt priority */
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value = 0x80 | (value >> 1);
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}
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s->gicd_ipriority[irq] = value;
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}
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static uint64_t gicd_read_irouter(GICv3State *s, MemTxAttrs attrs, int irq)
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{
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/* Read the value of GICD_IROUTER<n> for the specified interrupt,
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* honouring security state.
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*/
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return 0;
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}
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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/* RAZ/WI for NS accesses to secure interrupts */
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if (!gicv3_gicd_group_test(s, irq)) {
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if (gicd_ns_access(s, irq) != 3) {
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return 0;
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}
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}
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}
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return s->gicd_irouter[irq];
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}
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static void gicd_write_irouter(GICv3State *s, MemTxAttrs attrs, int irq,
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uint64_t val)
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{
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/* Write the value of GICD_IROUTER<n> for the specified interrupt,
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* honouring security state.
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*/
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return;
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}
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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/* RAZ/WI for NS accesses to secure interrupts */
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if (!gicv3_gicd_group_test(s, irq)) {
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if (gicd_ns_access(s, irq) != 3) {
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return;
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}
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}
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}
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s->gicd_irouter[irq] = val;
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gicv3_cache_target_cpustate(s, irq);
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gicv3_update(s, irq, 1);
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}
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/**
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* gicd_readb
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* gicd_readw
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* gicd_readl
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* gicd_readq
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* gicd_writeb
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* gicd_writew
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* gicd_writel
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* gicd_writeq
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*
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* Return %true if the operation succeeded, %false otherwise.
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*/
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static bool gicd_readb(GICv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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/* Most GICv3 distributor registers do not support byte accesses. */
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switch (offset) {
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case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
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case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
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case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
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/* This GIC implementation always has affinity routing enabled,
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* so these registers are all RAZ/WI.
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*/
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return true;
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case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
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*data = gicd_read_ipriorityr(s, attrs, offset - GICD_IPRIORITYR);
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return true;
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default:
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return false;
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}
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}
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static bool gicd_writeb(GICv3State *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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/* Most GICv3 distributor registers do not support byte accesses. */
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switch (offset) {
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case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
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case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
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case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
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/* This GIC implementation always has affinity routing enabled,
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* so these registers are all RAZ/WI.
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*/
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return true;
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case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
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{
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int irq = offset - GICD_IPRIORITYR;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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return true;
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}
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gicd_write_ipriorityr(s, attrs, irq, value);
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gicv3_update(s, irq, 1);
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return true;
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}
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default:
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return false;
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}
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}
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static bool gicd_readw(GICv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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/* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR
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* support 16 bit accesses, and those registers are all part of the
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* optional message-based SPI feature which this GIC does not currently
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* implement (ie for us GICD_TYPER.MBIS == 0), so for us they are
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* reserved.
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*/
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return false;
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}
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static bool gicd_writew(GICv3State *s, hwaddr offset,
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uint64_t value, MemTxAttrs attrs)
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{
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/* Only GICD_SETSPI_NSR, GICD_CLRSPI_NSR, GICD_SETSPI_SR and GICD_SETSPI_NSR
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* support 16 bit accesses, and those registers are all part of the
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* optional message-based SPI feature which this GIC does not currently
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* implement (ie for us GICD_TYPER.MBIS == 0), so for us they are
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* reserved.
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*/
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return false;
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}
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static bool gicd_readl(GICv3State *s, hwaddr offset,
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uint64_t *data, MemTxAttrs attrs)
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{
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/* Almost all GICv3 distributor registers are 32-bit.
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* Note that WO registers must return an UNKNOWN value on reads,
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* not an abort.
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*/
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switch (offset) {
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case GICD_CTLR:
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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/* The NS view of the GICD_CTLR sees only certain bits:
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* + bit [31] (RWP) is an alias of the Secure bit [31]
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* + bit [4] (ARE_NS) is an alias of Secure bit [5]
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* + bit [1] (EnableGrp1A) is an alias of Secure bit [1] if
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* NS affinity routing is enabled, otherwise RES0
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* + bit [0] (EnableGrp1) is an alias of Secure bit [1] if
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* NS affinity routing is not enabled, otherwise RES0
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* Since for QEMU affinity routing is always enabled
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* for both S and NS this means that bits [4] and [5] are
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* both always 1, and we can simply make the NS view
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* be bits 31, 4 and 1 of the S view.
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*/
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*data = s->gicd_ctlr & (GICD_CTLR_ARE_S |
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GICD_CTLR_EN_GRP1NS |
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GICD_CTLR_RWP);
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} else {
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*data = s->gicd_ctlr;
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}
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return true;
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case GICD_TYPER:
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{
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/* For this implementation:
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* No1N == 1 (1-of-N SPI interrupts not supported)
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* A3V == 1 (non-zero values of Affinity level 3 supported)
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* IDbits == 0xf (we support 16-bit interrupt identifiers)
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* DVIS == 1 (Direct virtual LPI injection supported) if GICv4
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* LPIS == 1 (LPIs are supported if affinity routing is enabled)
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* num_LPIs == 0b00000 (bits [15:11],Number of LPIs as indicated
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* by GICD_TYPER.IDbits)
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* MBIS == 0 (message-based SPIs not supported)
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* SecurityExtn == 1 if security extns supported
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* CPUNumber == 0 since for us ARE is always 1
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* ITLinesNumber == (num external irqs / 32) - 1
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*/
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int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
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/*
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* SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
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* "security extensions not supported" always implies DS == 1,
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* so we only need to check the DS bit.
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*/
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bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
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bool dvis = s->revision >= 4;
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*data = (1 << 25) | (1 << 24) | (dvis << 18) | (sec_extn << 10) |
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(s->lpi_enable << GICD_TYPER_LPIS_SHIFT) |
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(0xf << 19) | itlinesnumber;
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return true;
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}
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case GICD_IIDR:
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/* We claim to be an ARM r0p0 with a zero ProductID.
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* This is the same as an r0p0 GIC-500.
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*/
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*data = gicv3_iidr();
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return true;
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case GICD_STATUSR:
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/* RAZ/WI for us (this is an optional register and our implementation
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* does not track RO/WO/reserved violations to report them to the guest)
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*/
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*data = 0;
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return true;
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case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
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{
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int irq;
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if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
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*data = 0;
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return true;
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}
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/* RAZ/WI for SGIs, PPIs, unimplemented irqs */
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irq = (offset - GICD_IGROUPR) * 8;
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if (irq < GIC_INTERNAL || irq >= s->num_irq) {
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*data = 0;
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return true;
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}
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*data = *gic_bmp_ptr32(s->group, irq);
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return true;
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}
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case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
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*data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
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offset - GICD_ISENABLER);
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return true;
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case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
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*data = gicd_read_bitmap_reg(s, attrs, s->enabled, NULL,
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offset - GICD_ICENABLER);
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return true;
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case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
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*data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
|
|
offset - GICD_ISPENDR);
|
|
return true;
|
|
case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
|
|
*data = gicd_read_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
|
|
offset - GICD_ICPENDR);
|
|
return true;
|
|
case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
|
|
*data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
|
|
offset - GICD_ISACTIVER);
|
|
return true;
|
|
case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
|
|
*data = gicd_read_bitmap_reg(s, attrs, s->active, mask_nsacr_ge2,
|
|
offset - GICD_ICACTIVER);
|
|
return true;
|
|
case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
|
|
{
|
|
int i, irq = offset - GICD_IPRIORITYR;
|
|
uint32_t value = 0;
|
|
|
|
for (i = irq + 3; i >= irq; i--) {
|
|
value <<= 8;
|
|
value |= gicd_read_ipriorityr(s, attrs, i);
|
|
}
|
|
*data = value;
|
|
return true;
|
|
}
|
|
case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
|
|
/* RAZ/WI since affinity routing is always enabled */
|
|
*data = 0;
|
|
return true;
|
|
case GICD_ICFGR ... GICD_ICFGR + 0xff:
|
|
{
|
|
/* Here only the even bits are used; odd bits are RES0 */
|
|
int irq = (offset - GICD_ICFGR) * 4;
|
|
uint32_t value = 0;
|
|
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
*data = 0;
|
|
return true;
|
|
}
|
|
|
|
/* Since our edge_trigger bitmap is one bit per irq, we only need
|
|
* half of the 32-bit word, which we can then spread out
|
|
* into the odd bits.
|
|
*/
|
|
value = *gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f);
|
|
value &= mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
|
|
value = extract32(value, (irq & 0x1f) ? 16 : 0, 16);
|
|
value = half_shuffle32(value) << 1;
|
|
*data = value;
|
|
return true;
|
|
}
|
|
case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
|
|
{
|
|
int irq;
|
|
|
|
if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
|
|
/* RAZ/WI if security disabled, or if
|
|
* security enabled and this is an NS access
|
|
*/
|
|
*data = 0;
|
|
return true;
|
|
}
|
|
/* RAZ/WI for SGIs, PPIs, unimplemented irqs */
|
|
irq = (offset - GICD_IGRPMODR) * 8;
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
*data = 0;
|
|
return true;
|
|
}
|
|
*data = *gic_bmp_ptr32(s->grpmod, irq);
|
|
return true;
|
|
}
|
|
case GICD_NSACR ... GICD_NSACR + 0xff:
|
|
{
|
|
/* Two bits per interrupt */
|
|
int irq = (offset - GICD_NSACR) * 4;
|
|
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
*data = 0;
|
|
return true;
|
|
}
|
|
|
|
if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
|
|
/* RAZ/WI if security disabled, or if
|
|
* security enabled and this is an NS access
|
|
*/
|
|
*data = 0;
|
|
return true;
|
|
}
|
|
|
|
*data = s->gicd_nsacr[irq / 16];
|
|
return true;
|
|
}
|
|
case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
|
|
case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
|
|
/* RAZ/WI since affinity routing is always enabled */
|
|
*data = 0;
|
|
return true;
|
|
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
|
|
{
|
|
uint64_t r;
|
|
int irq = (offset - GICD_IROUTER) / 8;
|
|
|
|
r = gicd_read_irouter(s, attrs, irq);
|
|
if (offset & 7) {
|
|
*data = r >> 32;
|
|
} else {
|
|
*data = (uint32_t)r;
|
|
}
|
|
return true;
|
|
}
|
|
case GICD_IDREGS ... GICD_IDREGS + 0x2f:
|
|
/* ID registers */
|
|
*data = gicv3_idreg(s, offset - GICD_IDREGS, GICV3_PIDR0_DIST);
|
|
return true;
|
|
case GICD_SGIR:
|
|
/* WO registers, return unknown value */
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: invalid guest read from WO register at offset "
|
|
TARGET_FMT_plx "\n", __func__, offset);
|
|
*data = 0;
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool gicd_writel(GICv3State *s, hwaddr offset,
|
|
uint64_t value, MemTxAttrs attrs)
|
|
{
|
|
/* Almost all GICv3 distributor registers are 32-bit. Note that
|
|
* RO registers must ignore writes, not abort.
|
|
*/
|
|
|
|
switch (offset) {
|
|
case GICD_CTLR:
|
|
{
|
|
uint32_t mask;
|
|
/* GICv3 5.3.20 */
|
|
if (s->gicd_ctlr & GICD_CTLR_DS) {
|
|
/* With only one security state, E1NWF is RAZ/WI, DS is RAO/WI,
|
|
* ARE is RAO/WI (affinity routing always on), and only
|
|
* bits 0 and 1 (group enables) are writable.
|
|
*/
|
|
mask = GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1NS;
|
|
} else {
|
|
if (attrs.secure) {
|
|
/* for secure access:
|
|
* ARE_NS and ARE_S are RAO/WI (affinity routing always on)
|
|
* E1NWF is RAZ/WI (we don't support enable-1-of-n-wakeup)
|
|
*
|
|
* We can only modify bits[2:0] (the group enables).
|
|
*/
|
|
mask = GICD_CTLR_DS | GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1_ALL;
|
|
} else {
|
|
/* For non secure access ARE_NS is RAO/WI and EnableGrp1
|
|
* is RES0. The only writable bit is [1] (EnableGrp1A), which
|
|
* is an alias of the Secure bit [1].
|
|
*/
|
|
mask = GICD_CTLR_EN_GRP1NS;
|
|
}
|
|
}
|
|
s->gicd_ctlr = (s->gicd_ctlr & ~mask) | (value & mask);
|
|
if (value & mask & GICD_CTLR_DS) {
|
|
/* We just set DS, so the ARE_NS and EnG1S bits are now RES0.
|
|
* Note that this is a one-way transition because if DS is set
|
|
* then it's not writable, so it can only go back to 0 with a
|
|
* hardware reset.
|
|
*/
|
|
s->gicd_ctlr &= ~(GICD_CTLR_EN_GRP1S | GICD_CTLR_ARE_NS);
|
|
}
|
|
gicv3_full_update(s);
|
|
return true;
|
|
}
|
|
case GICD_STATUSR:
|
|
/* RAZ/WI for our implementation */
|
|
return true;
|
|
case GICD_IGROUPR ... GICD_IGROUPR + 0x7f:
|
|
{
|
|
int irq;
|
|
|
|
if (!attrs.secure && !(s->gicd_ctlr & GICD_CTLR_DS)) {
|
|
return true;
|
|
}
|
|
/* RAZ/WI for SGIs, PPIs, unimplemented irqs */
|
|
irq = (offset - GICD_IGROUPR) * 8;
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
return true;
|
|
}
|
|
*gic_bmp_ptr32(s->group, irq) = value;
|
|
gicv3_update(s, irq, 32);
|
|
return true;
|
|
}
|
|
case GICD_ISENABLER ... GICD_ISENABLER + 0x7f:
|
|
gicd_write_set_bitmap_reg(s, attrs, s->enabled, NULL,
|
|
offset - GICD_ISENABLER, value);
|
|
return true;
|
|
case GICD_ICENABLER ... GICD_ICENABLER + 0x7f:
|
|
gicd_write_clear_bitmap_reg(s, attrs, s->enabled, NULL,
|
|
offset - GICD_ICENABLER, value);
|
|
return true;
|
|
case GICD_ISPENDR ... GICD_ISPENDR + 0x7f:
|
|
gicd_write_set_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge1,
|
|
offset - GICD_ISPENDR, value);
|
|
return true;
|
|
case GICD_ICPENDR ... GICD_ICPENDR + 0x7f:
|
|
gicd_write_clear_bitmap_reg(s, attrs, s->pending, mask_nsacr_ge2,
|
|
offset - GICD_ICPENDR, value);
|
|
return true;
|
|
case GICD_ISACTIVER ... GICD_ISACTIVER + 0x7f:
|
|
gicd_write_set_bitmap_reg(s, attrs, s->active, NULL,
|
|
offset - GICD_ISACTIVER, value);
|
|
return true;
|
|
case GICD_ICACTIVER ... GICD_ICACTIVER + 0x7f:
|
|
gicd_write_clear_bitmap_reg(s, attrs, s->active, NULL,
|
|
offset - GICD_ICACTIVER, value);
|
|
return true;
|
|
case GICD_IPRIORITYR ... GICD_IPRIORITYR + 0x3ff:
|
|
{
|
|
int i, irq = offset - GICD_IPRIORITYR;
|
|
|
|
if (irq < GIC_INTERNAL || irq + 3 >= s->num_irq) {
|
|
return true;
|
|
}
|
|
|
|
for (i = irq; i < irq + 4; i++, value >>= 8) {
|
|
gicd_write_ipriorityr(s, attrs, i, value);
|
|
}
|
|
gicv3_update(s, irq, 4);
|
|
return true;
|
|
}
|
|
case GICD_ITARGETSR ... GICD_ITARGETSR + 0x3ff:
|
|
/* RAZ/WI since affinity routing is always enabled */
|
|
return true;
|
|
case GICD_ICFGR ... GICD_ICFGR + 0xff:
|
|
{
|
|
/* Here only the odd bits are used; even bits are RES0 */
|
|
int irq = (offset - GICD_ICFGR) * 4;
|
|
uint32_t mask, oldval;
|
|
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
return true;
|
|
}
|
|
|
|
/* Since our edge_trigger bitmap is one bit per irq, our input
|
|
* 32-bits will compress down into 16 bits which we need
|
|
* to write into the bitmap.
|
|
*/
|
|
value = half_unshuffle32(value >> 1);
|
|
mask = mask_group_and_nsacr(s, attrs, NULL, irq & ~0x1f);
|
|
if (irq & 0x1f) {
|
|
value <<= 16;
|
|
mask &= 0xffff0000U;
|
|
} else {
|
|
mask &= 0xffff;
|
|
}
|
|
oldval = *gic_bmp_ptr32(s->edge_trigger, (irq & ~0x1f));
|
|
value = (oldval & ~mask) | (value & mask);
|
|
*gic_bmp_ptr32(s->edge_trigger, irq & ~0x1f) = value;
|
|
return true;
|
|
}
|
|
case GICD_IGRPMODR ... GICD_IGRPMODR + 0xff:
|
|
{
|
|
int irq;
|
|
|
|
if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
|
|
/* RAZ/WI if security disabled, or if
|
|
* security enabled and this is an NS access
|
|
*/
|
|
return true;
|
|
}
|
|
/* RAZ/WI for SGIs, PPIs, unimplemented irqs */
|
|
irq = (offset - GICD_IGRPMODR) * 8;
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
return true;
|
|
}
|
|
*gic_bmp_ptr32(s->grpmod, irq) = value;
|
|
gicv3_update(s, irq, 32);
|
|
return true;
|
|
}
|
|
case GICD_NSACR ... GICD_NSACR + 0xff:
|
|
{
|
|
/* Two bits per interrupt */
|
|
int irq = (offset - GICD_NSACR) * 4;
|
|
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
return true;
|
|
}
|
|
|
|
if ((s->gicd_ctlr & GICD_CTLR_DS) || !attrs.secure) {
|
|
/* RAZ/WI if security disabled, or if
|
|
* security enabled and this is an NS access
|
|
*/
|
|
return true;
|
|
}
|
|
|
|
s->gicd_nsacr[irq / 16] = value;
|
|
/* No update required as this only affects access permission checks */
|
|
return true;
|
|
}
|
|
case GICD_SGIR:
|
|
/* RES0 if affinity routing is enabled */
|
|
return true;
|
|
case GICD_CPENDSGIR ... GICD_CPENDSGIR + 0xf:
|
|
case GICD_SPENDSGIR ... GICD_SPENDSGIR + 0xf:
|
|
/* RAZ/WI since affinity routing is always enabled */
|
|
return true;
|
|
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
|
|
{
|
|
uint64_t r;
|
|
int irq = (offset - GICD_IROUTER) / 8;
|
|
|
|
if (irq < GIC_INTERNAL || irq >= s->num_irq) {
|
|
return true;
|
|
}
|
|
|
|
/* Write half of the 64-bit register */
|
|
r = gicd_read_irouter(s, attrs, irq);
|
|
r = deposit64(r, (offset & 7) ? 32 : 0, 32, value);
|
|
gicd_write_irouter(s, attrs, irq, r);
|
|
return true;
|
|
}
|
|
case GICD_IDREGS ... GICD_IDREGS + 0x2f:
|
|
case GICD_TYPER:
|
|
case GICD_IIDR:
|
|
/* RO registers, ignore the write */
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: invalid guest write to RO register at offset "
|
|
TARGET_FMT_plx "\n", __func__, offset);
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool gicd_writeq(GICv3State *s, hwaddr offset,
|
|
uint64_t value, MemTxAttrs attrs)
|
|
{
|
|
/* Our only 64-bit registers are GICD_IROUTER<n> */
|
|
int irq;
|
|
|
|
switch (offset) {
|
|
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
|
|
irq = (offset - GICD_IROUTER) / 8;
|
|
gicd_write_irouter(s, attrs, irq, value);
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
static bool gicd_readq(GICv3State *s, hwaddr offset,
|
|
uint64_t *data, MemTxAttrs attrs)
|
|
{
|
|
/* Our only 64-bit registers are GICD_IROUTER<n> */
|
|
int irq;
|
|
|
|
switch (offset) {
|
|
case GICD_IROUTER ... GICD_IROUTER + 0x1fdf:
|
|
irq = (offset - GICD_IROUTER) / 8;
|
|
*data = gicd_read_irouter(s, attrs, irq);
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
MemTxResult gicv3_dist_read(void *opaque, hwaddr offset, uint64_t *data,
|
|
unsigned size, MemTxAttrs attrs)
|
|
{
|
|
GICv3State *s = (GICv3State *)opaque;
|
|
bool r;
|
|
|
|
switch (size) {
|
|
case 1:
|
|
r = gicd_readb(s, offset, data, attrs);
|
|
break;
|
|
case 2:
|
|
r = gicd_readw(s, offset, data, attrs);
|
|
break;
|
|
case 4:
|
|
r = gicd_readl(s, offset, data, attrs);
|
|
break;
|
|
case 8:
|
|
r = gicd_readq(s, offset, data, attrs);
|
|
break;
|
|
default:
|
|
r = false;
|
|
break;
|
|
}
|
|
|
|
if (!r) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: invalid guest read at offset " TARGET_FMT_plx
|
|
" size %u\n", __func__, offset, size);
|
|
trace_gicv3_dist_badread(offset, size, attrs.secure);
|
|
/* The spec requires that reserved registers are RAZ/WI;
|
|
* so use MEMTX_ERROR returns from leaf functions as a way to
|
|
* trigger the guest-error logging but don't return it to
|
|
* the caller, or we'll cause a spurious guest data abort.
|
|
*/
|
|
*data = 0;
|
|
} else {
|
|
trace_gicv3_dist_read(offset, *data, size, attrs.secure);
|
|
}
|
|
return MEMTX_OK;
|
|
}
|
|
|
|
MemTxResult gicv3_dist_write(void *opaque, hwaddr offset, uint64_t data,
|
|
unsigned size, MemTxAttrs attrs)
|
|
{
|
|
GICv3State *s = (GICv3State *)opaque;
|
|
bool r;
|
|
|
|
switch (size) {
|
|
case 1:
|
|
r = gicd_writeb(s, offset, data, attrs);
|
|
break;
|
|
case 2:
|
|
r = gicd_writew(s, offset, data, attrs);
|
|
break;
|
|
case 4:
|
|
r = gicd_writel(s, offset, data, attrs);
|
|
break;
|
|
case 8:
|
|
r = gicd_writeq(s, offset, data, attrs);
|
|
break;
|
|
default:
|
|
r = false;
|
|
break;
|
|
}
|
|
|
|
if (!r) {
|
|
qemu_log_mask(LOG_GUEST_ERROR,
|
|
"%s: invalid guest write at offset " TARGET_FMT_plx
|
|
" size %u\n", __func__, offset, size);
|
|
trace_gicv3_dist_badwrite(offset, data, size, attrs.secure);
|
|
/* The spec requires that reserved registers are RAZ/WI;
|
|
* so use MEMTX_ERROR returns from leaf functions as a way to
|
|
* trigger the guest-error logging but don't return it to
|
|
* the caller, or we'll cause a spurious guest data abort.
|
|
*/
|
|
} else {
|
|
trace_gicv3_dist_write(offset, data, size, attrs.secure);
|
|
}
|
|
return MEMTX_OK;
|
|
}
|
|
|
|
void gicv3_dist_set_irq(GICv3State *s, int irq, int level)
|
|
{
|
|
/* Update distributor state for a change in an external SPI input line */
|
|
if (level == gicv3_gicd_level_test(s, irq)) {
|
|
return;
|
|
}
|
|
|
|
trace_gicv3_dist_set_irq(irq, level);
|
|
|
|
gicv3_gicd_level_replace(s, irq, level);
|
|
|
|
if (level) {
|
|
/* 0->1 edges latch the pending bit for edge-triggered interrupts */
|
|
if (gicv3_gicd_edge_trigger_test(s, irq)) {
|
|
gicv3_gicd_pending_set(s, irq);
|
|
}
|
|
}
|
|
|
|
gicv3_update(s, irq, 1);
|
|
}
|