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373 lines
14 KiB
C
373 lines
14 KiB
C
/*
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* QEMU emulation of an AMD IOMMU (AMD-Vi)
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*
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* Copyright (C) 2011 Eduard - Gabriel Munteanu
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* Copyright (C) 2015, 2016 David Kiarie Kahurani
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef AMD_IOMMU_H
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#define AMD_IOMMU_H
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#include "hw/pci/pci.h"
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#include "hw/i386/x86-iommu.h"
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#include "qom/object.h"
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/* Capability registers */
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#define AMDVI_CAPAB_BAR_LOW 0x04
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#define AMDVI_CAPAB_BAR_HIGH 0x08
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#define AMDVI_CAPAB_RANGE 0x0C
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#define AMDVI_CAPAB_MISC 0x10
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#define AMDVI_CAPAB_SIZE 0x18
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#define AMDVI_CAPAB_REG_SIZE 0x04
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/* Capability header data */
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#define AMDVI_CAPAB_ID_SEC 0xf
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#define AMDVI_CAPAB_FLAT_EXT (1 << 28)
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#define AMDVI_CAPAB_EFR_SUP (1 << 27)
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#define AMDVI_CAPAB_FLAG_NPCACHE (1 << 26)
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#define AMDVI_CAPAB_FLAG_HTTUNNEL (1 << 25)
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#define AMDVI_CAPAB_FLAG_IOTLBSUP (1 << 24)
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#define AMDVI_CAPAB_INIT_TYPE (3 << 16)
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/* No. of used MMIO registers */
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#define AMDVI_MMIO_REGS_HIGH 7
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#define AMDVI_MMIO_REGS_LOW 8
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/* MMIO registers */
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#define AMDVI_MMIO_DEVICE_TABLE 0x0000
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#define AMDVI_MMIO_COMMAND_BASE 0x0008
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#define AMDVI_MMIO_EVENT_BASE 0x0010
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#define AMDVI_MMIO_CONTROL 0x0018
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#define AMDVI_MMIO_EXCL_BASE 0x0020
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#define AMDVI_MMIO_EXCL_LIMIT 0x0028
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#define AMDVI_MMIO_EXT_FEATURES 0x0030
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#define AMDVI_MMIO_COMMAND_HEAD 0x2000
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#define AMDVI_MMIO_COMMAND_TAIL 0x2008
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#define AMDVI_MMIO_EVENT_HEAD 0x2010
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#define AMDVI_MMIO_EVENT_TAIL 0x2018
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#define AMDVI_MMIO_STATUS 0x2020
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#define AMDVI_MMIO_PPR_BASE 0x0038
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#define AMDVI_MMIO_PPR_HEAD 0x2030
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#define AMDVI_MMIO_PPR_TAIL 0x2038
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#define AMDVI_MMIO_SIZE 0x4000
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#define AMDVI_MMIO_DEVTAB_SIZE_MASK ((1ULL << 12) - 1)
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#define AMDVI_MMIO_DEVTAB_BASE_MASK (((1ULL << 52) - 1) & ~ \
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AMDVI_MMIO_DEVTAB_SIZE_MASK)
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#define AMDVI_MMIO_DEVTAB_ENTRY_SIZE 32
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#define AMDVI_MMIO_DEVTAB_SIZE_UNIT 4096
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/* some of this are similar but just for readability */
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#define AMDVI_MMIO_CMDBUF_SIZE_BYTE (AMDVI_MMIO_COMMAND_BASE + 7)
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#define AMDVI_MMIO_CMDBUF_SIZE_MASK 0x0f
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#define AMDVI_MMIO_CMDBUF_BASE_MASK AMDVI_MMIO_DEVTAB_BASE_MASK
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#define AMDVI_MMIO_CMDBUF_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f)
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#define AMDVI_MMIO_CMDBUF_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK
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#define AMDVI_MMIO_EVTLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7)
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#define AMDVI_MMIO_EVTLOG_SIZE_MASK AMDVI_MMIO_CMDBUF_SIZE_MASK
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#define AMDVI_MMIO_EVTLOG_BASE_MASK AMDVI_MMIO_CMDBUF_BASE_MASK
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#define AMDVI_MMIO_EVTLOG_HEAD_MASK (((1ULL << 19) - 1) & ~0x0f)
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#define AMDVI_MMIO_EVTLOG_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK
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#define AMDVI_MMIO_PPRLOG_SIZE_BYTE (AMDVI_MMIO_EVENT_BASE + 7)
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#define AMDVI_MMIO_PPRLOG_HEAD_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK
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#define AMDVI_MMIO_PPRLOG_TAIL_MASK AMDVI_MMIO_EVTLOG_HEAD_MASK
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#define AMDVI_MMIO_PPRLOG_BASE_MASK AMDVI_MMIO_EVTLOG_BASE_MASK
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#define AMDVI_MMIO_PPRLOG_SIZE_MASK AMDVI_MMIO_EVTLOG_SIZE_MASK
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#define AMDVI_MMIO_EXCL_ENABLED_MASK (1ULL << 0)
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#define AMDVI_MMIO_EXCL_ALLOW_MASK (1ULL << 1)
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#define AMDVI_MMIO_EXCL_LIMIT_MASK AMDVI_MMIO_DEVTAB_BASE_MASK
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#define AMDVI_MMIO_EXCL_LIMIT_LOW 0xfff
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/* mmio control register flags */
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#define AMDVI_MMIO_CONTROL_AMDVIEN (1ULL << 0)
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#define AMDVI_MMIO_CONTROL_HTTUNEN (1ULL << 1)
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#define AMDVI_MMIO_CONTROL_EVENTLOGEN (1ULL << 2)
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#define AMDVI_MMIO_CONTROL_EVENTINTEN (1ULL << 3)
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#define AMDVI_MMIO_CONTROL_COMWAITINTEN (1ULL << 4)
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#define AMDVI_MMIO_CONTROL_CMDBUFLEN (1ULL << 12)
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#define AMDVI_MMIO_CONTROL_GAEN (1ULL << 17)
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/* MMIO status register bits */
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#define AMDVI_MMIO_STATUS_CMDBUF_RUN (1 << 4)
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#define AMDVI_MMIO_STATUS_EVT_RUN (1 << 3)
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#define AMDVI_MMIO_STATUS_COMP_INT (1 << 2)
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#define AMDVI_MMIO_STATUS_EVT_OVF (1 << 0)
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#define AMDVI_CMDBUF_ID_BYTE 0x07
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#define AMDVI_CMDBUF_ID_RSHIFT 4
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#define AMDVI_CMD_COMPLETION_WAIT 0x01
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#define AMDVI_CMD_INVAL_DEVTAB_ENTRY 0x02
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#define AMDVI_CMD_INVAL_AMDVI_PAGES 0x03
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#define AMDVI_CMD_INVAL_IOTLB_PAGES 0x04
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#define AMDVI_CMD_INVAL_INTR_TABLE 0x05
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#define AMDVI_CMD_PREFETCH_AMDVI_PAGES 0x06
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#define AMDVI_CMD_COMPLETE_PPR_REQUEST 0x07
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#define AMDVI_CMD_INVAL_AMDVI_ALL 0x08
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#define AMDVI_DEVTAB_ENTRY_SIZE 32
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/* Device table entry bits 0:63 */
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#define AMDVI_DEV_VALID (1ULL << 0)
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#define AMDVI_DEV_TRANSLATION_VALID (1ULL << 1)
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#define AMDVI_DEV_MODE_MASK 0x7
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#define AMDVI_DEV_MODE_RSHIFT 9
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#define AMDVI_DEV_PT_ROOT_MASK 0xffffffffff000
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#define AMDVI_DEV_PT_ROOT_RSHIFT 12
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#define AMDVI_DEV_PERM_SHIFT 61
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#define AMDVI_DEV_PERM_READ (1ULL << 61)
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#define AMDVI_DEV_PERM_WRITE (1ULL << 62)
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/* Device table entry bits 64:127 */
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#define AMDVI_DEV_DOMID_ID_MASK ((1ULL << 16) - 1)
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/* Event codes and flags, as stored in the info field */
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#define AMDVI_EVENT_ILLEGAL_DEVTAB_ENTRY (0x1U << 12)
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#define AMDVI_EVENT_IOPF (0x2U << 12)
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#define AMDVI_EVENT_IOPF_I (1U << 3)
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#define AMDVI_EVENT_DEV_TAB_HW_ERROR (0x3U << 12)
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#define AMDVI_EVENT_PAGE_TAB_HW_ERROR (0x4U << 12)
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#define AMDVI_EVENT_ILLEGAL_COMMAND_ERROR (0x5U << 12)
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#define AMDVI_EVENT_COMMAND_HW_ERROR (0x6U << 12)
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#define AMDVI_EVENT_LEN 16
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#define AMDVI_PERM_READ (1 << 0)
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#define AMDVI_PERM_WRITE (1 << 1)
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#define AMDVI_FEATURE_PREFETCH (1ULL << 0) /* page prefetch */
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#define AMDVI_FEATURE_PPR (1ULL << 1) /* PPR Support */
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#define AMDVI_FEATURE_GT (1ULL << 4) /* Guest Translation */
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#define AMDVI_FEATURE_IA (1ULL << 6) /* inval all support */
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#define AMDVI_FEATURE_GA (1ULL << 7) /* guest VAPIC support */
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#define AMDVI_FEATURE_HE (1ULL << 8) /* hardware error regs */
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#define AMDVI_FEATURE_PC (1ULL << 9) /* Perf counters */
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/* reserved DTE bits */
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#define AMDVI_DTE_LOWER_QUAD_RESERVED 0x80300000000000fc
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#define AMDVI_DTE_MIDDLE_QUAD_RESERVED 0x0000000000000100
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#define AMDVI_DTE_UPPER_QUAD_RESERVED 0x08f0000000000000
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/* AMDVI paging mode */
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#define AMDVI_GATS_MODE (2ULL << 12)
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#define AMDVI_HATS_MODE (2ULL << 10)
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/* IOTLB */
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#define AMDVI_IOTLB_MAX_SIZE 1024
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#define AMDVI_DEVID_SHIFT 36
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/* extended feature support */
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#define AMDVI_EXT_FEATURES (AMDVI_FEATURE_PREFETCH | AMDVI_FEATURE_PPR | \
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AMDVI_FEATURE_IA | AMDVI_FEATURE_GT | AMDVI_FEATURE_HE | \
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AMDVI_GATS_MODE | AMDVI_HATS_MODE | AMDVI_FEATURE_GA)
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/* capabilities header */
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#define AMDVI_CAPAB_FEATURES (AMDVI_CAPAB_FLAT_EXT | \
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AMDVI_CAPAB_FLAG_NPCACHE | AMDVI_CAPAB_FLAG_IOTLBSUP \
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| AMDVI_CAPAB_ID_SEC | AMDVI_CAPAB_INIT_TYPE | \
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AMDVI_CAPAB_FLAG_HTTUNNEL | AMDVI_CAPAB_EFR_SUP)
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/* AMDVI default address */
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#define AMDVI_BASE_ADDR 0xfed80000
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/* page management constants */
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#define AMDVI_PAGE_SHIFT 12
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#define AMDVI_PAGE_SIZE (1ULL << AMDVI_PAGE_SHIFT)
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#define AMDVI_PAGE_SHIFT_4K 12
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#define AMDVI_PAGE_MASK_4K (~((1ULL << AMDVI_PAGE_SHIFT_4K) - 1))
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#define AMDVI_MAX_VA_ADDR (48UL << 5)
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#define AMDVI_MAX_PH_ADDR (40UL << 8)
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#define AMDVI_MAX_GVA_ADDR (48UL << 15)
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/* Completion Wait data size */
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#define AMDVI_COMPLETION_DATA_SIZE 8
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#define AMDVI_COMMAND_SIZE 16
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/* Completion Wait data size */
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#define AMDVI_COMPLETION_DATA_SIZE 8
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#define AMDVI_COMMAND_SIZE 16
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#define AMDVI_INT_ADDR_FIRST 0xfee00000
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#define AMDVI_INT_ADDR_LAST 0xfeefffff
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#define AMDVI_INT_ADDR_SIZE (AMDVI_INT_ADDR_LAST - AMDVI_INT_ADDR_FIRST + 1)
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#define AMDVI_MSI_ADDR_HI_MASK (0xffffffff00000000ULL)
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#define AMDVI_MSI_ADDR_LO_MASK (0x00000000ffffffffULL)
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/* SB IOAPIC is always on this device in AMD systems */
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#define AMDVI_IOAPIC_SB_DEVID PCI_BUILD_BDF(0, PCI_DEVFN(0x14, 0))
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/* Interrupt remapping errors */
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#define AMDVI_IR_ERR 0x1
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#define AMDVI_IR_GET_IRTE 0x2
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#define AMDVI_IR_TARGET_ABORT 0x3
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/* Interrupt remapping */
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#define AMDVI_IR_REMAP_ENABLE 1ULL
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#define AMDVI_IR_INTCTL_SHIFT 60
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#define AMDVI_IR_INTCTL_ABORT 0
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#define AMDVI_IR_INTCTL_PASS 1
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#define AMDVI_IR_INTCTL_REMAP 2
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#define AMDVI_IR_PHYS_ADDR_MASK (((1ULL << 45) - 1) << 6)
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/* MSI data 10:0 bits (section 2.2.5.1 Fig 14) */
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#define AMDVI_IRTE_OFFSET 0x7ff
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/* Delivery mode of MSI data (same as IOAPIC deilver mode encoding) */
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#define AMDVI_IOAPIC_INT_TYPE_FIXED 0x0
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#define AMDVI_IOAPIC_INT_TYPE_ARBITRATED 0x1
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#define AMDVI_IOAPIC_INT_TYPE_SMI 0x2
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#define AMDVI_IOAPIC_INT_TYPE_NMI 0x4
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#define AMDVI_IOAPIC_INT_TYPE_INIT 0x5
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#define AMDVI_IOAPIC_INT_TYPE_EINT 0x7
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/* Pass through interrupt */
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#define AMDVI_DEV_INT_PASS_MASK (1ULL << 56)
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#define AMDVI_DEV_EINT_PASS_MASK (1ULL << 57)
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#define AMDVI_DEV_NMI_PASS_MASK (1ULL << 58)
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#define AMDVI_DEV_LINT0_PASS_MASK (1ULL << 62)
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#define AMDVI_DEV_LINT1_PASS_MASK (1ULL << 63)
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/* Interrupt remapping table fields (Guest VAPIC not enabled) */
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union irte {
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uint32_t val;
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struct {
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uint32_t valid:1,
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no_fault:1,
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int_type:3,
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rq_eoi:1,
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dm:1,
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guest_mode:1,
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destination:8,
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vector:8,
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rsvd:8;
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} fields;
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};
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/* Interrupt remapping table fields (Guest VAPIC is enabled) */
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union irte_ga_lo {
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uint64_t val;
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/* For int remapping */
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struct {
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uint64_t valid:1,
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no_fault:1,
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/* ------ */
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int_type:3,
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rq_eoi:1,
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dm:1,
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/* ------ */
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guest_mode:1,
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destination:8,
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rsvd_1:48;
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} fields_remap;
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};
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union irte_ga_hi {
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uint64_t val;
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struct {
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uint64_t vector:8,
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rsvd_2:56;
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} fields;
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};
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struct irte_ga {
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union irte_ga_lo lo;
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union irte_ga_hi hi;
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};
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#define TYPE_AMD_IOMMU_DEVICE "amd-iommu"
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OBJECT_DECLARE_SIMPLE_TYPE(AMDVIState, AMD_IOMMU_DEVICE)
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#define TYPE_AMD_IOMMU_PCI "AMDVI-PCI"
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#define TYPE_AMD_IOMMU_MEMORY_REGION "amd-iommu-iommu-memory-region"
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typedef struct AMDVIAddressSpace AMDVIAddressSpace;
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/* functions to steal PCI config space */
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typedef struct AMDVIPCIState {
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PCIDevice dev; /* The PCI device itself */
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} AMDVIPCIState;
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struct AMDVIState {
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X86IOMMUState iommu; /* IOMMU bus device */
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AMDVIPCIState pci; /* IOMMU PCI device */
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uint32_t version;
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uint32_t capab_offset; /* capability offset pointer */
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uint64_t mmio_addr;
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uint32_t devid; /* auto-assigned devid */
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bool enabled; /* IOMMU enabled */
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bool ats_enabled; /* address translation enabled */
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bool cmdbuf_enabled; /* command buffer enabled */
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bool evtlog_enabled; /* event log enabled */
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bool excl_enabled;
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hwaddr devtab; /* base address device table */
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size_t devtab_len; /* device table length */
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hwaddr cmdbuf; /* command buffer base address */
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uint64_t cmdbuf_len; /* command buffer length */
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uint32_t cmdbuf_head; /* current IOMMU read position */
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uint32_t cmdbuf_tail; /* next Software write position */
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bool completion_wait_intr;
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hwaddr evtlog; /* base address event log */
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bool evtlog_intr;
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uint32_t evtlog_len; /* event log length */
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uint32_t evtlog_head; /* current IOMMU write position */
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uint32_t evtlog_tail; /* current Software read position */
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/* unused for now */
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hwaddr excl_base; /* base DVA - IOMMU exclusion range */
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hwaddr excl_limit; /* limit of IOMMU exclusion range */
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bool excl_allow; /* translate accesses to the exclusion range */
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bool excl_enable; /* exclusion range enabled */
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hwaddr ppr_log; /* base address ppr log */
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uint32_t pprlog_len; /* ppr log len */
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uint32_t pprlog_head; /* ppr log head */
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uint32_t pprlog_tail; /* ppr log tail */
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MemoryRegion mmio; /* MMIO region */
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uint8_t mmior[AMDVI_MMIO_SIZE]; /* read/write MMIO */
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uint8_t w1cmask[AMDVI_MMIO_SIZE]; /* read/write 1 clear mask */
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uint8_t romask[AMDVI_MMIO_SIZE]; /* MMIO read/only mask */
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bool mmio_enabled;
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/* for each served device */
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AMDVIAddressSpace **address_spaces[PCI_BUS_MAX];
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/* IOTLB */
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GHashTable *iotlb;
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/* Interrupt remapping */
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bool ga_enabled;
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};
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#endif
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