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739 lines
22 KiB
C
739 lines
22 KiB
C
/*
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* Exynos4210 UART Emulation
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*
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* Copyright (C) 2011 Samsung Electronics Co Ltd.
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* Maksim Kozlov, <m.kozlov@samsung.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "migration/vmstate.h"
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#include "qapi/error.h"
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#include "qemu/error-report.h"
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#include "qemu/module.h"
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#include "qemu/timer.h"
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#include "chardev/char-fe.h"
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#include "chardev/char-serial.h"
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#include "hw/arm/exynos4210.h"
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#include "hw/irq.h"
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#include "hw/qdev-properties.h"
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#include "hw/qdev-properties-system.h"
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#include "trace.h"
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#include "qom/object.h"
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/*
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* Offsets for UART registers relative to SFR base address
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* for UARTn
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*
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*/
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#define ULCON 0x0000 /* Line Control */
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#define UCON 0x0004 /* Control */
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#define UFCON 0x0008 /* FIFO Control */
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#define UMCON 0x000C /* Modem Control */
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#define UTRSTAT 0x0010 /* Tx/Rx Status */
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#define UERSTAT 0x0014 /* UART Error Status */
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#define UFSTAT 0x0018 /* FIFO Status */
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#define UMSTAT 0x001C /* Modem Status */
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#define UTXH 0x0020 /* Transmit Buffer */
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#define URXH 0x0024 /* Receive Buffer */
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#define UBRDIV 0x0028 /* Baud Rate Divisor */
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#define UFRACVAL 0x002C /* Divisor Fractional Value */
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#define UINTP 0x0030 /* Interrupt Pending */
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#define UINTSP 0x0034 /* Interrupt Source Pending */
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#define UINTM 0x0038 /* Interrupt Mask */
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/*
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* for indexing register in the uint32_t array
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*
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* 'reg' - register offset (see offsets definitions above)
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*
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*/
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#define I_(reg) (reg / sizeof(uint32_t))
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typedef struct Exynos4210UartReg {
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const char *name; /* the only reason is the debug output */
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hwaddr offset;
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uint32_t reset_value;
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} Exynos4210UartReg;
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static const Exynos4210UartReg exynos4210_uart_regs[] = {
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{"ULCON", ULCON, 0x00000000},
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{"UCON", UCON, 0x00003000},
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{"UFCON", UFCON, 0x00000000},
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{"UMCON", UMCON, 0x00000000},
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{"UTRSTAT", UTRSTAT, 0x00000006}, /* RO */
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{"UERSTAT", UERSTAT, 0x00000000}, /* RO */
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{"UFSTAT", UFSTAT, 0x00000000}, /* RO */
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{"UMSTAT", UMSTAT, 0x00000000}, /* RO */
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{"UTXH", UTXH, 0x5c5c5c5c}, /* WO, undefined reset value*/
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{"URXH", URXH, 0x00000000}, /* RO */
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{"UBRDIV", UBRDIV, 0x00000000},
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{"UFRACVAL", UFRACVAL, 0x00000000},
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{"UINTP", UINTP, 0x00000000},
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{"UINTSP", UINTSP, 0x00000000},
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{"UINTM", UINTM, 0x00000000},
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};
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#define EXYNOS4210_UART_REGS_MEM_SIZE 0x3C
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/* UART FIFO Control */
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#define UFCON_FIFO_ENABLE 0x1
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#define UFCON_Rx_FIFO_RESET 0x2
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#define UFCON_Tx_FIFO_RESET 0x4
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT 8
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#define UFCON_Tx_FIFO_TRIGGER_LEVEL (7 << UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT)
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT 4
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#define UFCON_Rx_FIFO_TRIGGER_LEVEL (7 << UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT)
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/* Uart FIFO Status */
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#define UFSTAT_Rx_FIFO_COUNT 0xff
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#define UFSTAT_Rx_FIFO_FULL 0x100
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#define UFSTAT_Rx_FIFO_ERROR 0x200
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#define UFSTAT_Tx_FIFO_COUNT_SHIFT 16
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#define UFSTAT_Tx_FIFO_COUNT (0xff << UFSTAT_Tx_FIFO_COUNT_SHIFT)
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#define UFSTAT_Tx_FIFO_FULL_SHIFT 24
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#define UFSTAT_Tx_FIFO_FULL (1 << UFSTAT_Tx_FIFO_FULL_SHIFT)
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/* UART Interrupt Source Pending */
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#define UINTSP_RXD 0x1 /* Receive interrupt */
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#define UINTSP_ERROR 0x2 /* Error interrupt */
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#define UINTSP_TXD 0x4 /* Transmit interrupt */
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#define UINTSP_MODEM 0x8 /* Modem interrupt */
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/* UART Line Control */
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#define ULCON_IR_MODE_SHIFT 6
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#define ULCON_PARITY_SHIFT 3
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#define ULCON_STOP_BIT_SHIFT 1
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/* UART Tx/Rx Status */
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#define UTRSTAT_Rx_TIMEOUT 0x8
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#define UTRSTAT_TRANSMITTER_EMPTY 0x4
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#define UTRSTAT_Tx_BUFFER_EMPTY 0x2
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#define UTRSTAT_Rx_BUFFER_DATA_READY 0x1
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/* UART Error Status */
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#define UERSTAT_OVERRUN 0x1
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#define UERSTAT_PARITY 0x2
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#define UERSTAT_FRAME 0x4
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#define UERSTAT_BREAK 0x8
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typedef struct {
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uint8_t *data;
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uint32_t sp, rp; /* store and retrieve pointers */
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uint32_t size;
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} Exynos4210UartFIFO;
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#define TYPE_EXYNOS4210_UART "exynos4210.uart"
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OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210UartState, EXYNOS4210_UART)
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struct Exynos4210UartState {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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uint32_t reg[EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)];
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Exynos4210UartFIFO rx;
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Exynos4210UartFIFO tx;
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QEMUTimer *fifo_timeout_timer;
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uint64_t wordtime; /* word time in ns */
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CharBackend chr;
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qemu_irq irq;
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qemu_irq dmairq;
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uint32_t channel;
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};
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/* Used only for tracing */
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static const char *exynos4210_uart_regname(hwaddr offset)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
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if (offset == exynos4210_uart_regs[i].offset) {
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return exynos4210_uart_regs[i].name;
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}
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}
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return NULL;
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}
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static void fifo_store(Exynos4210UartFIFO *q, uint8_t ch)
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{
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q->data[q->sp] = ch;
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q->sp = (q->sp + 1) % q->size;
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}
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static uint8_t fifo_retrieve(Exynos4210UartFIFO *q)
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{
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uint8_t ret = q->data[q->rp];
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q->rp = (q->rp + 1) % q->size;
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return ret;
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}
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static int fifo_elements_number(const Exynos4210UartFIFO *q)
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{
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if (q->sp < q->rp) {
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return q->size - q->rp + q->sp;
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}
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return q->sp - q->rp;
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}
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static int fifo_empty_elements_number(const Exynos4210UartFIFO *q)
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{
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return q->size - fifo_elements_number(q);
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}
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static void fifo_reset(Exynos4210UartFIFO *q)
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{
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g_free(q->data);
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q->data = NULL;
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q->data = g_malloc0(q->size);
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q->sp = 0;
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q->rp = 0;
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}
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static uint32_t exynos4210_uart_FIFO_trigger_level(uint32_t channel,
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uint32_t reg)
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{
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uint32_t level;
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switch (channel) {
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case 0:
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level = reg * 32;
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break;
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case 1:
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case 4:
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level = reg * 8;
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break;
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case 2:
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case 3:
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level = reg * 2;
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break;
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default:
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level = 0;
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trace_exynos_uart_channel_error(channel);
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break;
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}
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return level;
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}
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static uint32_t
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exynos4210_uart_Tx_FIFO_trigger_level(const Exynos4210UartState *s)
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{
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uint32_t reg;
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reg = (s->reg[I_(UFCON)] & UFCON_Tx_FIFO_TRIGGER_LEVEL) >>
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UFCON_Tx_FIFO_TRIGGER_LEVEL_SHIFT;
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return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
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}
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static uint32_t
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exynos4210_uart_Rx_FIFO_trigger_level(const Exynos4210UartState *s)
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{
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uint32_t reg;
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reg = ((s->reg[I_(UFCON)] & UFCON_Rx_FIFO_TRIGGER_LEVEL) >>
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UFCON_Rx_FIFO_TRIGGER_LEVEL_SHIFT) + 1;
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return exynos4210_uart_FIFO_trigger_level(s->channel, reg);
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}
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/*
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* Update Rx DMA busy signal if Rx DMA is enabled. For simplicity,
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* mark DMA as busy if DMA is enabled and the receive buffer is empty.
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*/
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static void exynos4210_uart_update_dmabusy(Exynos4210UartState *s)
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{
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bool rx_dma_enabled = (s->reg[I_(UCON)] & 0x03) == 0x02;
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uint32_t count = fifo_elements_number(&s->rx);
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if (rx_dma_enabled && !count) {
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qemu_irq_raise(s->dmairq);
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trace_exynos_uart_dmabusy(s->channel);
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} else {
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qemu_irq_lower(s->dmairq);
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trace_exynos_uart_dmaready(s->channel);
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}
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}
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static void exynos4210_uart_update_irq(Exynos4210UartState *s)
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{
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/*
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* The Tx interrupt is always requested if the number of data in the
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* transmit FIFO is smaller than the trigger level.
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*/
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if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
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uint32_t count = (s->reg[I_(UFSTAT)] & UFSTAT_Tx_FIFO_COUNT) >>
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UFSTAT_Tx_FIFO_COUNT_SHIFT;
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if (count <= exynos4210_uart_Tx_FIFO_trigger_level(s)) {
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s->reg[I_(UINTSP)] |= UINTSP_TXD;
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}
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/*
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* Rx interrupt if trigger level is reached or if rx timeout
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* interrupt is disabled and there is data in the receive buffer
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*/
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count = fifo_elements_number(&s->rx);
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if ((count && !(s->reg[I_(UCON)] & 0x80)) ||
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count >= exynos4210_uart_Rx_FIFO_trigger_level(s)) {
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exynos4210_uart_update_dmabusy(s);
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s->reg[I_(UINTSP)] |= UINTSP_RXD;
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timer_del(s->fifo_timeout_timer);
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}
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} else if (s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) {
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exynos4210_uart_update_dmabusy(s);
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s->reg[I_(UINTSP)] |= UINTSP_RXD;
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}
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s->reg[I_(UINTP)] = s->reg[I_(UINTSP)] & ~s->reg[I_(UINTM)];
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if (s->reg[I_(UINTP)]) {
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qemu_irq_raise(s->irq);
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trace_exynos_uart_irq_raised(s->channel, s->reg[I_(UINTP)]);
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} else {
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qemu_irq_lower(s->irq);
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trace_exynos_uart_irq_lowered(s->channel);
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}
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}
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static void exynos4210_uart_timeout_int(void *opaque)
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{
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Exynos4210UartState *s = opaque;
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trace_exynos_uart_rx_timeout(s->channel, s->reg[I_(UTRSTAT)],
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s->reg[I_(UINTSP)]);
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if ((s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY) ||
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(s->reg[I_(UCON)] & (1 << 11))) {
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s->reg[I_(UINTSP)] |= UINTSP_RXD;
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s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_TIMEOUT;
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exynos4210_uart_update_dmabusy(s);
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exynos4210_uart_update_irq(s);
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}
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}
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static void exynos4210_uart_update_parameters(Exynos4210UartState *s)
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{
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int speed, parity, data_bits, stop_bits;
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QEMUSerialSetParams ssp;
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uint64_t uclk_rate;
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if (s->reg[I_(UBRDIV)] == 0) {
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return;
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}
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if (s->reg[I_(ULCON)] & 0x20) {
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if (s->reg[I_(ULCON)] & 0x28) {
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parity = 'E';
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} else {
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parity = 'O';
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}
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} else {
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parity = 'N';
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}
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if (s->reg[I_(ULCON)] & 0x4) {
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stop_bits = 2;
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} else {
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stop_bits = 1;
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}
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data_bits = (s->reg[I_(ULCON)] & 0x3) + 5;
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uclk_rate = 24000000;
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speed = uclk_rate / ((16 * (s->reg[I_(UBRDIV)]) & 0xffff) +
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(s->reg[I_(UFRACVAL)] & 0x7) + 16);
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ssp.speed = speed;
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ssp.parity = parity;
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ssp.data_bits = data_bits;
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ssp.stop_bits = stop_bits;
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s->wordtime = NANOSECONDS_PER_SECOND * (data_bits + stop_bits + 1) / speed;
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qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp);
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trace_exynos_uart_update_params(
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s->channel, speed, parity, data_bits, stop_bits, s->wordtime);
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}
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static void exynos4210_uart_rx_timeout_set(Exynos4210UartState *s)
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{
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if (s->reg[I_(UCON)] & 0x80) {
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uint32_t timeout = ((s->reg[I_(UCON)] >> 12) & 0x0f) * s->wordtime;
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timer_mod(s->fifo_timeout_timer,
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qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + timeout);
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} else {
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timer_del(s->fifo_timeout_timer);
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}
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}
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static void exynos4210_uart_write(void *opaque, hwaddr offset,
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uint64_t val, unsigned size)
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{
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Exynos4210UartState *s = (Exynos4210UartState *)opaque;
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uint8_t ch;
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trace_exynos_uart_write(s->channel, offset,
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exynos4210_uart_regname(offset), val);
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switch (offset) {
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case ULCON:
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case UBRDIV:
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case UFRACVAL:
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s->reg[I_(offset)] = val;
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exynos4210_uart_update_parameters(s);
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break;
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case UFCON:
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s->reg[I_(UFCON)] = val;
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if (val & UFCON_Rx_FIFO_RESET) {
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fifo_reset(&s->rx);
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s->reg[I_(UFCON)] &= ~UFCON_Rx_FIFO_RESET;
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trace_exynos_uart_rx_fifo_reset(s->channel);
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}
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if (val & UFCON_Tx_FIFO_RESET) {
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fifo_reset(&s->tx);
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s->reg[I_(UFCON)] &= ~UFCON_Tx_FIFO_RESET;
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trace_exynos_uart_tx_fifo_reset(s->channel);
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}
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break;
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case UTXH:
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if (qemu_chr_fe_backend_connected(&s->chr)) {
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s->reg[I_(UTRSTAT)] &= ~(UTRSTAT_TRANSMITTER_EMPTY |
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UTRSTAT_Tx_BUFFER_EMPTY);
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ch = (uint8_t)val;
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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trace_exynos_uart_tx(s->channel, ch);
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s->reg[I_(UTRSTAT)] |= UTRSTAT_TRANSMITTER_EMPTY |
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UTRSTAT_Tx_BUFFER_EMPTY;
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s->reg[I_(UINTSP)] |= UINTSP_TXD;
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exynos4210_uart_update_irq(s);
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}
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break;
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case UINTP:
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s->reg[I_(UINTP)] &= ~val;
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s->reg[I_(UINTSP)] &= ~val;
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trace_exynos_uart_intclr(s->channel, s->reg[I_(UINTP)]);
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exynos4210_uart_update_irq(s);
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break;
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case UTRSTAT:
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if (val & UTRSTAT_Rx_TIMEOUT) {
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s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_TIMEOUT;
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}
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break;
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case UERSTAT:
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case UFSTAT:
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case UMSTAT:
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case URXH:
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trace_exynos_uart_ro_write(
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s->channel, exynos4210_uart_regname(offset), offset);
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break;
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case UINTSP:
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s->reg[I_(UINTSP)] &= ~val;
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break;
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case UINTM:
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s->reg[I_(UINTM)] = val;
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exynos4210_uart_update_irq(s);
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break;
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case UCON:
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case UMCON:
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default:
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s->reg[I_(offset)] = val;
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break;
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}
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}
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static uint64_t exynos4210_uart_read(void *opaque, hwaddr offset,
|
|
unsigned size)
|
|
{
|
|
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
|
uint32_t res;
|
|
|
|
switch (offset) {
|
|
case UERSTAT: /* Read Only */
|
|
res = s->reg[I_(UERSTAT)];
|
|
s->reg[I_(UERSTAT)] = 0;
|
|
trace_exynos_uart_read(s->channel, offset,
|
|
exynos4210_uart_regname(offset), res);
|
|
return res;
|
|
case UFSTAT: /* Read Only */
|
|
s->reg[I_(UFSTAT)] = fifo_elements_number(&s->rx) & 0xff;
|
|
if (fifo_empty_elements_number(&s->rx) == 0) {
|
|
s->reg[I_(UFSTAT)] |= UFSTAT_Rx_FIFO_FULL;
|
|
s->reg[I_(UFSTAT)] &= ~0xff;
|
|
}
|
|
trace_exynos_uart_read(s->channel, offset,
|
|
exynos4210_uart_regname(offset),
|
|
s->reg[I_(UFSTAT)]);
|
|
return s->reg[I_(UFSTAT)];
|
|
case URXH:
|
|
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
|
if (fifo_elements_number(&s->rx)) {
|
|
res = fifo_retrieve(&s->rx);
|
|
trace_exynos_uart_rx(s->channel, res);
|
|
if (!fifo_elements_number(&s->rx)) {
|
|
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
|
|
} else {
|
|
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
|
}
|
|
} else {
|
|
trace_exynos_uart_rx_error(s->channel);
|
|
s->reg[I_(UINTSP)] |= UINTSP_ERROR;
|
|
exynos4210_uart_update_irq(s);
|
|
res = 0;
|
|
}
|
|
} else {
|
|
s->reg[I_(UTRSTAT)] &= ~UTRSTAT_Rx_BUFFER_DATA_READY;
|
|
res = s->reg[I_(URXH)];
|
|
}
|
|
qemu_chr_fe_accept_input(&s->chr);
|
|
exynos4210_uart_update_dmabusy(s);
|
|
trace_exynos_uart_read(s->channel, offset,
|
|
exynos4210_uart_regname(offset), res);
|
|
return res;
|
|
case UTXH:
|
|
trace_exynos_uart_wo_read(s->channel, exynos4210_uart_regname(offset),
|
|
offset);
|
|
break;
|
|
default:
|
|
trace_exynos_uart_read(s->channel, offset,
|
|
exynos4210_uart_regname(offset),
|
|
s->reg[I_(offset)]);
|
|
return s->reg[I_(offset)];
|
|
}
|
|
|
|
trace_exynos_uart_read(s->channel, offset, exynos4210_uart_regname(offset),
|
|
0);
|
|
return 0;
|
|
}
|
|
|
|
static const MemoryRegionOps exynos4210_uart_ops = {
|
|
.read = exynos4210_uart_read,
|
|
.write = exynos4210_uart_write,
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
.valid = {
|
|
.max_access_size = 4,
|
|
.unaligned = false
|
|
},
|
|
};
|
|
|
|
static int exynos4210_uart_can_receive(void *opaque)
|
|
{
|
|
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
|
|
|
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
|
return fifo_empty_elements_number(&s->rx);
|
|
} else {
|
|
return !(s->reg[I_(UTRSTAT)] & UTRSTAT_Rx_BUFFER_DATA_READY);
|
|
}
|
|
}
|
|
|
|
static void exynos4210_uart_receive(void *opaque, const uint8_t *buf, int size)
|
|
{
|
|
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
|
int i;
|
|
|
|
if (s->reg[I_(UFCON)] & UFCON_FIFO_ENABLE) {
|
|
if (fifo_empty_elements_number(&s->rx) < size) {
|
|
size = fifo_empty_elements_number(&s->rx);
|
|
s->reg[I_(UINTSP)] |= UINTSP_ERROR;
|
|
}
|
|
for (i = 0; i < size; i++) {
|
|
fifo_store(&s->rx, buf[i]);
|
|
}
|
|
exynos4210_uart_rx_timeout_set(s);
|
|
} else {
|
|
s->reg[I_(URXH)] = buf[0];
|
|
}
|
|
s->reg[I_(UTRSTAT)] |= UTRSTAT_Rx_BUFFER_DATA_READY;
|
|
|
|
exynos4210_uart_update_irq(s);
|
|
}
|
|
|
|
|
|
static void exynos4210_uart_event(void *opaque, QEMUChrEvent event)
|
|
{
|
|
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
|
|
|
if (event == CHR_EVENT_BREAK) {
|
|
/* When the RxDn is held in logic 0, then a null byte is pushed into the
|
|
* fifo */
|
|
fifo_store(&s->rx, '\0');
|
|
s->reg[I_(UERSTAT)] |= UERSTAT_BREAK;
|
|
exynos4210_uart_update_irq(s);
|
|
}
|
|
}
|
|
|
|
|
|
static void exynos4210_uart_reset(DeviceState *dev)
|
|
{
|
|
Exynos4210UartState *s = EXYNOS4210_UART(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < ARRAY_SIZE(exynos4210_uart_regs); i++) {
|
|
s->reg[I_(exynos4210_uart_regs[i].offset)] =
|
|
exynos4210_uart_regs[i].reset_value;
|
|
}
|
|
|
|
fifo_reset(&s->rx);
|
|
fifo_reset(&s->tx);
|
|
|
|
trace_exynos_uart_rxsize(s->channel, s->rx.size);
|
|
}
|
|
|
|
static int exynos4210_uart_post_load(void *opaque, int version_id)
|
|
{
|
|
Exynos4210UartState *s = (Exynos4210UartState *)opaque;
|
|
|
|
exynos4210_uart_update_parameters(s);
|
|
exynos4210_uart_rx_timeout_set(s);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const VMStateDescription vmstate_exynos4210_uart_fifo = {
|
|
.name = "exynos4210.uart.fifo",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_UINT32(sp, Exynos4210UartFIFO),
|
|
VMSTATE_UINT32(rp, Exynos4210UartFIFO),
|
|
VMSTATE_VBUFFER_UINT32(data, Exynos4210UartFIFO, 1, NULL, size),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
static const VMStateDescription vmstate_exynos4210_uart = {
|
|
.name = "exynos4210.uart",
|
|
.version_id = 1,
|
|
.minimum_version_id = 1,
|
|
.post_load = exynos4210_uart_post_load,
|
|
.fields = (VMStateField[]) {
|
|
VMSTATE_STRUCT(rx, Exynos4210UartState, 1,
|
|
vmstate_exynos4210_uart_fifo, Exynos4210UartFIFO),
|
|
VMSTATE_UINT32_ARRAY(reg, Exynos4210UartState,
|
|
EXYNOS4210_UART_REGS_MEM_SIZE / sizeof(uint32_t)),
|
|
VMSTATE_END_OF_LIST()
|
|
}
|
|
};
|
|
|
|
DeviceState *exynos4210_uart_create(hwaddr addr,
|
|
int fifo_size,
|
|
int channel,
|
|
Chardev *chr,
|
|
qemu_irq irq)
|
|
{
|
|
DeviceState *dev;
|
|
SysBusDevice *bus;
|
|
|
|
dev = qdev_new(TYPE_EXYNOS4210_UART);
|
|
|
|
qdev_prop_set_chr(dev, "chardev", chr);
|
|
qdev_prop_set_uint32(dev, "channel", channel);
|
|
qdev_prop_set_uint32(dev, "rx-size", fifo_size);
|
|
qdev_prop_set_uint32(dev, "tx-size", fifo_size);
|
|
|
|
bus = SYS_BUS_DEVICE(dev);
|
|
sysbus_realize_and_unref(bus, &error_fatal);
|
|
if (addr != (hwaddr)-1) {
|
|
sysbus_mmio_map(bus, 0, addr);
|
|
}
|
|
sysbus_connect_irq(bus, 0, irq);
|
|
|
|
return dev;
|
|
}
|
|
|
|
static void exynos4210_uart_init(Object *obj)
|
|
{
|
|
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
|
|
Exynos4210UartState *s = EXYNOS4210_UART(dev);
|
|
|
|
s->wordtime = NANOSECONDS_PER_SECOND * 10 / 9600;
|
|
|
|
/* memory mapping */
|
|
memory_region_init_io(&s->iomem, obj, &exynos4210_uart_ops, s,
|
|
"exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
|
|
sysbus_init_mmio(dev, &s->iomem);
|
|
|
|
sysbus_init_irq(dev, &s->irq);
|
|
sysbus_init_irq(dev, &s->dmairq);
|
|
}
|
|
|
|
static void exynos4210_uart_realize(DeviceState *dev, Error **errp)
|
|
{
|
|
Exynos4210UartState *s = EXYNOS4210_UART(dev);
|
|
|
|
s->fifo_timeout_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
|
|
exynos4210_uart_timeout_int, s);
|
|
|
|
qemu_chr_fe_set_handlers(&s->chr, exynos4210_uart_can_receive,
|
|
exynos4210_uart_receive, exynos4210_uart_event,
|
|
NULL, s, NULL, true);
|
|
}
|
|
|
|
static Property exynos4210_uart_properties[] = {
|
|
DEFINE_PROP_CHR("chardev", Exynos4210UartState, chr),
|
|
DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0),
|
|
DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16),
|
|
DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void exynos4210_uart_class_init(ObjectClass *klass, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
dc->realize = exynos4210_uart_realize;
|
|
dc->reset = exynos4210_uart_reset;
|
|
device_class_set_props(dc, exynos4210_uart_properties);
|
|
dc->vmsd = &vmstate_exynos4210_uart;
|
|
}
|
|
|
|
static const TypeInfo exynos4210_uart_info = {
|
|
.name = TYPE_EXYNOS4210_UART,
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
.instance_size = sizeof(Exynos4210UartState),
|
|
.instance_init = exynos4210_uart_init,
|
|
.class_init = exynos4210_uart_class_init,
|
|
};
|
|
|
|
static void exynos4210_uart_register(void)
|
|
{
|
|
type_register_static(&exynos4210_uart_info);
|
|
}
|
|
|
|
type_init(exynos4210_uart_register)
|