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670 lines
23 KiB
C
670 lines
23 KiB
C
/*
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* ASPEED SoC family
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*
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* Andrew Jeffery <andrew@aj.id.au>
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* Jeremy Kerr <jk@ozlabs.org>
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*
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* Copyright 2016 IBM Corp.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/units.h"
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#include "qapi/error.h"
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#include "hw/misc/unimp.h"
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#include "hw/arm/aspeed_soc.h"
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#include "hw/char/serial.h"
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#include "qemu/module.h"
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#include "qemu/error-report.h"
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#include "hw/i2c/aspeed_i2c.h"
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#include "net/net.h"
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#include "sysemu/sysemu.h"
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#define ASPEED_SOC_IOMEM_SIZE 0x00200000
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static const hwaddr aspeed_soc_ast2400_memmap[] = {
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[ASPEED_DEV_IOMEM] = 0x1E600000,
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[ASPEED_DEV_FMC] = 0x1E620000,
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[ASPEED_DEV_SPI1] = 0x1E630000,
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[ASPEED_DEV_EHCI1] = 0x1E6A1000,
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[ASPEED_DEV_VIC] = 0x1E6C0000,
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[ASPEED_DEV_SDMC] = 0x1E6E0000,
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[ASPEED_DEV_SCU] = 0x1E6E2000,
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[ASPEED_DEV_HACE] = 0x1E6E3000,
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[ASPEED_DEV_XDMA] = 0x1E6E7000,
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[ASPEED_DEV_VIDEO] = 0x1E700000,
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[ASPEED_DEV_ADC] = 0x1E6E9000,
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[ASPEED_DEV_SRAM] = 0x1E720000,
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[ASPEED_DEV_SDHCI] = 0x1E740000,
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[ASPEED_DEV_GPIO] = 0x1E780000,
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[ASPEED_DEV_RTC] = 0x1E781000,
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[ASPEED_DEV_TIMER1] = 0x1E782000,
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[ASPEED_DEV_WDT] = 0x1E785000,
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[ASPEED_DEV_PWM] = 0x1E786000,
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[ASPEED_DEV_LPC] = 0x1E789000,
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[ASPEED_DEV_IBT] = 0x1E789140,
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[ASPEED_DEV_I2C] = 0x1E78A000,
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[ASPEED_DEV_PECI] = 0x1E78B000,
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[ASPEED_DEV_ETH1] = 0x1E660000,
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[ASPEED_DEV_ETH2] = 0x1E680000,
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[ASPEED_DEV_UART1] = 0x1E783000,
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[ASPEED_DEV_UART2] = 0x1E78D000,
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[ASPEED_DEV_UART3] = 0x1E78E000,
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[ASPEED_DEV_UART4] = 0x1E78F000,
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[ASPEED_DEV_UART5] = 0x1E784000,
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[ASPEED_DEV_VUART] = 0x1E787000,
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[ASPEED_DEV_SDRAM] = 0x40000000,
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};
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static const hwaddr aspeed_soc_ast2500_memmap[] = {
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[ASPEED_DEV_IOMEM] = 0x1E600000,
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[ASPEED_DEV_FMC] = 0x1E620000,
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[ASPEED_DEV_SPI1] = 0x1E630000,
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[ASPEED_DEV_SPI2] = 0x1E631000,
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[ASPEED_DEV_EHCI1] = 0x1E6A1000,
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[ASPEED_DEV_EHCI2] = 0x1E6A3000,
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[ASPEED_DEV_VIC] = 0x1E6C0000,
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[ASPEED_DEV_SDMC] = 0x1E6E0000,
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[ASPEED_DEV_SCU] = 0x1E6E2000,
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[ASPEED_DEV_HACE] = 0x1E6E3000,
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[ASPEED_DEV_XDMA] = 0x1E6E7000,
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[ASPEED_DEV_ADC] = 0x1E6E9000,
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[ASPEED_DEV_VIDEO] = 0x1E700000,
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[ASPEED_DEV_SRAM] = 0x1E720000,
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[ASPEED_DEV_SDHCI] = 0x1E740000,
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[ASPEED_DEV_GPIO] = 0x1E780000,
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[ASPEED_DEV_RTC] = 0x1E781000,
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[ASPEED_DEV_TIMER1] = 0x1E782000,
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[ASPEED_DEV_WDT] = 0x1E785000,
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[ASPEED_DEV_PWM] = 0x1E786000,
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[ASPEED_DEV_LPC] = 0x1E789000,
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[ASPEED_DEV_IBT] = 0x1E789140,
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[ASPEED_DEV_I2C] = 0x1E78A000,
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[ASPEED_DEV_PECI] = 0x1E78B000,
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[ASPEED_DEV_ETH1] = 0x1E660000,
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[ASPEED_DEV_ETH2] = 0x1E680000,
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[ASPEED_DEV_UART1] = 0x1E783000,
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[ASPEED_DEV_UART2] = 0x1E78D000,
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[ASPEED_DEV_UART3] = 0x1E78E000,
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[ASPEED_DEV_UART4] = 0x1E78F000,
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[ASPEED_DEV_UART5] = 0x1E784000,
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[ASPEED_DEV_VUART] = 0x1E787000,
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[ASPEED_DEV_SDRAM] = 0x80000000,
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};
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static const int aspeed_soc_ast2400_irqmap[] = {
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[ASPEED_DEV_UART1] = 9,
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[ASPEED_DEV_UART2] = 32,
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[ASPEED_DEV_UART3] = 33,
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[ASPEED_DEV_UART4] = 34,
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[ASPEED_DEV_UART5] = 10,
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[ASPEED_DEV_VUART] = 8,
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[ASPEED_DEV_FMC] = 19,
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[ASPEED_DEV_EHCI1] = 5,
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[ASPEED_DEV_EHCI2] = 13,
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[ASPEED_DEV_SDMC] = 0,
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[ASPEED_DEV_SCU] = 21,
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[ASPEED_DEV_ADC] = 31,
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[ASPEED_DEV_GPIO] = 20,
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[ASPEED_DEV_RTC] = 22,
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[ASPEED_DEV_TIMER1] = 16,
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[ASPEED_DEV_TIMER2] = 17,
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[ASPEED_DEV_TIMER3] = 18,
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[ASPEED_DEV_TIMER4] = 35,
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[ASPEED_DEV_TIMER5] = 36,
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[ASPEED_DEV_TIMER6] = 37,
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[ASPEED_DEV_TIMER7] = 38,
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[ASPEED_DEV_TIMER8] = 39,
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[ASPEED_DEV_WDT] = 27,
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[ASPEED_DEV_PWM] = 28,
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[ASPEED_DEV_LPC] = 8,
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[ASPEED_DEV_I2C] = 12,
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[ASPEED_DEV_PECI] = 15,
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[ASPEED_DEV_ETH1] = 2,
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[ASPEED_DEV_ETH2] = 3,
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[ASPEED_DEV_XDMA] = 6,
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[ASPEED_DEV_SDHCI] = 26,
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[ASPEED_DEV_HACE] = 4,
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};
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#define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap
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static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev)
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{
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]);
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}
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static void aspeed_soc_init(Object *obj)
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{
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AspeedSoCState *s = ASPEED_SOC(obj);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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int i;
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char socname[8];
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char typename[64];
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if (sscanf(sc->name, "%7s", socname) != 1) {
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g_assert_not_reached();
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}
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for (i = 0; i < sc->num_cpus; i++) {
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object_initialize_child(obj, "cpu[*]", &s->cpu[i], sc->cpu_type);
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}
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snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname);
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object_initialize_child(obj, "scu", &s->scu, typename);
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qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev",
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sc->silicon_rev);
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object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu),
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"hw-strap1");
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object_property_add_alias(obj, "hw-strap2", OBJECT(&s->scu),
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"hw-strap2");
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object_property_add_alias(obj, "hw-prot-key", OBJECT(&s->scu),
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"hw-prot-key");
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object_initialize_child(obj, "vic", &s->vic, TYPE_ASPEED_VIC);
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object_initialize_child(obj, "rtc", &s->rtc, TYPE_ASPEED_RTC);
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snprintf(typename, sizeof(typename), "aspeed.timer-%s", socname);
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object_initialize_child(obj, "timerctrl", &s->timerctrl, typename);
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snprintf(typename, sizeof(typename), "aspeed.adc-%s", socname);
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object_initialize_child(obj, "adc", &s->adc, typename);
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snprintf(typename, sizeof(typename), "aspeed.i2c-%s", socname);
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object_initialize_child(obj, "i2c", &s->i2c, typename);
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object_initialize_child(obj, "peci", &s->peci, TYPE_ASPEED_PECI);
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snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname);
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object_initialize_child(obj, "fmc", &s->fmc, typename);
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for (i = 0; i < sc->spis_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname);
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object_initialize_child(obj, "spi[*]", &s->spi[i], typename);
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}
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for (i = 0; i < sc->ehcis_num; i++) {
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object_initialize_child(obj, "ehci[*]", &s->ehci[i],
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TYPE_PLATFORM_EHCI);
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}
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snprintf(typename, sizeof(typename), "aspeed.sdmc-%s", socname);
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object_initialize_child(obj, "sdmc", &s->sdmc, typename);
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object_property_add_alias(obj, "ram-size", OBJECT(&s->sdmc),
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"ram-size");
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for (i = 0; i < sc->wdts_num; i++) {
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snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname);
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object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename);
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}
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for (i = 0; i < sc->macs_num; i++) {
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object_initialize_child(obj, "ftgmac100[*]", &s->ftgmac100[i],
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TYPE_FTGMAC100);
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}
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for (i = 0; i < sc->uarts_num; i++) {
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object_initialize_child(obj, "uart[*]", &s->uart[i], TYPE_SERIAL_MM);
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}
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snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname);
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object_initialize_child(obj, "xdma", &s->xdma, typename);
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snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname);
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object_initialize_child(obj, "gpio", &s->gpio, typename);
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object_initialize_child(obj, "sdc", &s->sdhci, TYPE_ASPEED_SDHCI);
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object_property_set_int(OBJECT(&s->sdhci), "num-slots", 2, &error_abort);
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/* Init sd card slot class here so that they're under the correct parent */
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for (i = 0; i < ASPEED_SDHCI_NUM_SLOTS; ++i) {
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object_initialize_child(obj, "sdhci[*]", &s->sdhci.slots[i],
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TYPE_SYSBUS_SDHCI);
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}
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object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC);
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snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname);
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object_initialize_child(obj, "hace", &s->hace, typename);
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object_initialize_child(obj, "iomem", &s->iomem, TYPE_UNIMPLEMENTED_DEVICE);
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object_initialize_child(obj, "video", &s->video, TYPE_UNIMPLEMENTED_DEVICE);
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}
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static void aspeed_soc_realize(DeviceState *dev, Error **errp)
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{
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int i;
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AspeedSoCState *s = ASPEED_SOC(dev);
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AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
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Error *err = NULL;
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g_autofree char *sram_name = NULL;
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/* IO space */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->iomem), "aspeed.io",
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sc->memmap[ASPEED_DEV_IOMEM],
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ASPEED_SOC_IOMEM_SIZE);
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/* Video engine stub */
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aspeed_mmio_map_unimplemented(s, SYS_BUS_DEVICE(&s->video), "aspeed.video",
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sc->memmap[ASPEED_DEV_VIDEO], 0x1000);
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/* CPU */
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for (i = 0; i < sc->num_cpus; i++) {
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object_property_set_link(OBJECT(&s->cpu[i]), "memory",
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OBJECT(s->memory), &error_abort);
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if (!qdev_realize(DEVICE(&s->cpu[i]), NULL, errp)) {
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return;
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}
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}
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/* SRAM */
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sram_name = g_strdup_printf("aspeed.sram.%d", CPU(&s->cpu[0])->cpu_index);
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memory_region_init_ram(&s->sram, OBJECT(s), sram_name, sc->sram_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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memory_region_add_subregion(s->memory,
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sc->memmap[ASPEED_DEV_SRAM], &s->sram);
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/* SCU */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->scu), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->scu), 0, sc->memmap[ASPEED_DEV_SCU]);
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/* VIC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->vic), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->vic), 0, sc->memmap[ASPEED_DEV_VIC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 0,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_IRQ));
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->vic), 1,
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qdev_get_gpio_in(DEVICE(&s->cpu), ARM_CPU_FIQ));
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/* RTC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->rtc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->rtc), 0, sc->memmap[ASPEED_DEV_RTC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->rtc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_RTC));
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/* Timer */
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object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->timerctrl), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->timerctrl), 0,
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sc->memmap[ASPEED_DEV_TIMER1]);
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for (i = 0; i < ASPEED_TIMER_NR_TIMERS; i++) {
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qemu_irq irq = aspeed_soc_get_irq(s, ASPEED_DEV_TIMER1 + i);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->timerctrl), i, irq);
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}
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/* ADC */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->adc), 0, sc->memmap[ASPEED_DEV_ADC]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_ADC));
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/* UART */
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if (!aspeed_soc_uart_realize(s, errp)) {
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return;
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}
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/* I2C */
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object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->i2c), 0, sc->memmap[ASPEED_DEV_I2C]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_I2C));
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/* PECI */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->peci), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->peci), 0,
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sc->memmap[ASPEED_DEV_PECI]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->peci), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_PECI));
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/* FMC, The number of CS is set at the board level */
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object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr),
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&error_abort);
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 0, sc->memmap[ASPEED_DEV_FMC]);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->fmc), 1,
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ASPEED_SMC_GET_CLASS(&s->fmc)->flash_window_base);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->fmc), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_FMC));
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/* SPI */
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for (i = 0; i < sc->spis_num; i++) {
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 0,
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sc->memmap[ASPEED_DEV_SPI1 + i]);
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->spi[i]), 1,
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ASPEED_SMC_GET_CLASS(&s->spi[i])->flash_window_base);
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}
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/* EHCI */
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for (i = 0; i < sc->ehcis_num; i++) {
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->ehci[i]), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ehci[i]), 0,
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sc->memmap[ASPEED_DEV_EHCI1 + i]);
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sysbus_connect_irq(SYS_BUS_DEVICE(&s->ehci[i]), 0,
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aspeed_soc_get_irq(s, ASPEED_DEV_EHCI1 + i));
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}
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/* SDMC - SDRAM Memory Controller */
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if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdmc), errp)) {
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return;
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}
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aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdmc), 0,
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sc->memmap[ASPEED_DEV_SDMC]);
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/* Watch dog */
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for (i = 0; i < sc->wdts_num; i++) {
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AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(&s->wdt[i]);
|
|
|
|
object_property_set_link(OBJECT(&s->wdt[i]), "scu", OBJECT(&s->scu),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->wdt[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->wdt[i]), 0,
|
|
sc->memmap[ASPEED_DEV_WDT] + i * awc->offset);
|
|
}
|
|
|
|
/* RAM */
|
|
if (!aspeed_soc_dram_init(s, errp)) {
|
|
return;
|
|
}
|
|
|
|
/* Net */
|
|
for (i = 0; i < sc->macs_num; i++) {
|
|
object_property_set_bool(OBJECT(&s->ftgmac100[i]), "aspeed", true,
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->ftgmac100[i]), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
sc->memmap[ASPEED_DEV_ETH1 + i]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->ftgmac100[i]), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_ETH1 + i));
|
|
}
|
|
|
|
/* XDMA */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->xdma), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->xdma), 0,
|
|
sc->memmap[ASPEED_DEV_XDMA]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_XDMA));
|
|
|
|
/* GPIO */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->gpio), 0,
|
|
sc->memmap[ASPEED_DEV_GPIO]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_GPIO));
|
|
|
|
/* SDHCI */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->sdhci), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
sc->memmap[ASPEED_DEV_SDHCI]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_SDHCI));
|
|
|
|
/* LPC */
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->lpc), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->lpc), 0, sc->memmap[ASPEED_DEV_LPC]);
|
|
|
|
/* Connect the LPC IRQ to the VIC */
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_LPC));
|
|
|
|
/*
|
|
* On the AST2400 and AST2500 the one LPC IRQ is shared between all of the
|
|
* subdevices. Connect the LPC subdevice IRQs to the LPC controller IRQ (by
|
|
* contrast, on the AST2600, the subdevice IRQs are connected straight to
|
|
* the GIC).
|
|
*
|
|
* LPC subdevice IRQ sources are offset from 1 because the shared IRQ output
|
|
* to the VIC is at offset 0.
|
|
*/
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_1,
|
|
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_1));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_2,
|
|
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_2));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_3,
|
|
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_3));
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4,
|
|
qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4));
|
|
|
|
/* HACE */
|
|
object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr),
|
|
&error_abort);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) {
|
|
return;
|
|
}
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(&s->hace), 0,
|
|
sc->memmap[ASPEED_DEV_HACE]);
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0,
|
|
aspeed_soc_get_irq(s, ASPEED_DEV_HACE));
|
|
}
|
|
static Property aspeed_soc_properties[] = {
|
|
DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION,
|
|
MemoryRegion *),
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
};
|
|
|
|
static void aspeed_soc_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
DeviceClass *dc = DEVICE_CLASS(oc);
|
|
|
|
dc->realize = aspeed_soc_realize;
|
|
/* Reason: Uses serial_hds and nd_table in realize() directly */
|
|
dc->user_creatable = false;
|
|
device_class_set_props(dc, aspeed_soc_properties);
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_type_info = {
|
|
.name = TYPE_ASPEED_SOC,
|
|
.parent = TYPE_DEVICE,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_size = sizeof(AspeedSoCClass),
|
|
.class_init = aspeed_soc_class_init,
|
|
.abstract = true,
|
|
};
|
|
|
|
static void aspeed_soc_ast2400_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
sc->name = "ast2400-a1";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("arm926");
|
|
sc->silicon_rev = AST2400_A1_SILICON_REV;
|
|
sc->sram_size = 0x8000;
|
|
sc->spis_num = 1;
|
|
sc->ehcis_num = 1;
|
|
sc->wdts_num = 2;
|
|
sc->macs_num = 2;
|
|
sc->uarts_num = 5;
|
|
sc->irqmap = aspeed_soc_ast2400_irqmap;
|
|
sc->memmap = aspeed_soc_ast2400_memmap;
|
|
sc->num_cpus = 1;
|
|
sc->get_irq = aspeed_soc_ast2400_get_irq;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2400_type_info = {
|
|
.name = "ast2400-a1",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_init = aspeed_soc_init,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_init = aspeed_soc_ast2400_class_init,
|
|
};
|
|
|
|
static void aspeed_soc_ast2500_class_init(ObjectClass *oc, void *data)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_CLASS(oc);
|
|
|
|
sc->name = "ast2500-a1";
|
|
sc->cpu_type = ARM_CPU_TYPE_NAME("arm1176");
|
|
sc->silicon_rev = AST2500_A1_SILICON_REV;
|
|
sc->sram_size = 0x9000;
|
|
sc->spis_num = 2;
|
|
sc->ehcis_num = 2;
|
|
sc->wdts_num = 3;
|
|
sc->macs_num = 2;
|
|
sc->uarts_num = 5;
|
|
sc->irqmap = aspeed_soc_ast2500_irqmap;
|
|
sc->memmap = aspeed_soc_ast2500_memmap;
|
|
sc->num_cpus = 1;
|
|
sc->get_irq = aspeed_soc_ast2400_get_irq;
|
|
}
|
|
|
|
static const TypeInfo aspeed_soc_ast2500_type_info = {
|
|
.name = "ast2500-a1",
|
|
.parent = TYPE_ASPEED_SOC,
|
|
.instance_init = aspeed_soc_init,
|
|
.instance_size = sizeof(AspeedSoCState),
|
|
.class_init = aspeed_soc_ast2500_class_init,
|
|
};
|
|
static void aspeed_soc_register_types(void)
|
|
{
|
|
type_register_static(&aspeed_soc_type_info);
|
|
type_register_static(&aspeed_soc_ast2400_type_info);
|
|
type_register_static(&aspeed_soc_ast2500_type_info);
|
|
};
|
|
|
|
type_init(aspeed_soc_register_types);
|
|
|
|
qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev)
|
|
{
|
|
return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev);
|
|
}
|
|
|
|
bool aspeed_soc_uart_realize(AspeedSoCState *s, Error **errp)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
|
|
SerialMM *smm;
|
|
|
|
for (int i = 0, uart = ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart++) {
|
|
smm = &s->uart[i];
|
|
|
|
/* Chardev property is set by the machine. */
|
|
qdev_prop_set_uint8(DEVICE(smm), "regshift", 2);
|
|
qdev_prop_set_uint32(DEVICE(smm), "baudbase", 38400);
|
|
qdev_set_legacy_instance_id(DEVICE(smm), sc->memmap[uart], 2);
|
|
qdev_prop_set_uint8(DEVICE(smm), "endianness", DEVICE_LITTLE_ENDIAN);
|
|
if (!sysbus_realize(SYS_BUS_DEVICE(smm), errp)) {
|
|
return false;
|
|
}
|
|
|
|
sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, aspeed_soc_get_irq(s, uart));
|
|
aspeed_mmio_map(s, SYS_BUS_DEVICE(smm), 0, sc->memmap[uart]);
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
void aspeed_soc_uart_set_chr(AspeedSoCState *s, int dev, Chardev *chr)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
|
|
int i = dev - ASPEED_DEV_UART1;
|
|
|
|
g_assert(0 <= i && i < ARRAY_SIZE(s->uart) && i < sc->uarts_num);
|
|
qdev_prop_set_chr(DEVICE(&s->uart[i]), "chardev", chr);
|
|
}
|
|
|
|
/*
|
|
* SDMC should be realized first to get correct RAM size and max size
|
|
* values
|
|
*/
|
|
bool aspeed_soc_dram_init(AspeedSoCState *s, Error **errp)
|
|
{
|
|
AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s);
|
|
ram_addr_t ram_size, max_ram_size;
|
|
|
|
ram_size = object_property_get_uint(OBJECT(&s->sdmc), "ram-size",
|
|
&error_abort);
|
|
max_ram_size = object_property_get_uint(OBJECT(&s->sdmc), "max-ram-size",
|
|
&error_abort);
|
|
|
|
memory_region_init(&s->dram_container, OBJECT(s), "ram-container",
|
|
max_ram_size);
|
|
memory_region_add_subregion(&s->dram_container, 0, s->dram_mr);
|
|
|
|
/*
|
|
* Add a memory region beyond the RAM region to let firmwares scan
|
|
* the address space with load/store and guess how much RAM the
|
|
* SoC has.
|
|
*/
|
|
if (ram_size < max_ram_size) {
|
|
DeviceState *dev = qdev_new(TYPE_UNIMPLEMENTED_DEVICE);
|
|
|
|
qdev_prop_set_string(dev, "name", "ram-empty");
|
|
qdev_prop_set_uint64(dev, "size", max_ram_size - ram_size);
|
|
if (!sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), errp)) {
|
|
return false;
|
|
}
|
|
|
|
memory_region_add_subregion_overlap(&s->dram_container, ram_size,
|
|
sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0), -1000);
|
|
}
|
|
|
|
memory_region_add_subregion(s->memory,
|
|
sc->memmap[ASPEED_DEV_SDRAM], &s->dram_container);
|
|
return true;
|
|
}
|
|
|
|
void aspeed_mmio_map(AspeedSoCState *s, SysBusDevice *dev, int n, hwaddr addr)
|
|
{
|
|
memory_region_add_subregion(s->memory, addr,
|
|
sysbus_mmio_get_region(dev, n));
|
|
}
|
|
|
|
void aspeed_mmio_map_unimplemented(AspeedSoCState *s, SysBusDevice *dev,
|
|
const char *name, hwaddr addr, uint64_t size)
|
|
{
|
|
qdev_prop_set_string(DEVICE(dev), "name", name);
|
|
qdev_prop_set_uint64(DEVICE(dev), "size", size);
|
|
sysbus_realize(dev, &error_abort);
|
|
|
|
memory_region_add_subregion_overlap(s->memory, addr,
|
|
sysbus_mmio_get_region(dev, 0), -1000);
|
|
}
|